Advanced Synthesis Settings Dialog Box

To access, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).

Allows you to change advanced settings that impact the synthesis of your design. Use the Search field to quickly locate any full or partial option name. The Optimization mode setting enables various combinations of these settings to achieve your design goals.

Table 1. Advanced Synthesis Settings (1 of 13)

Option

Description

Allow Any RAM Size for Recognition

Allows the Compiler to infer RAMs of any size, even if the RAMs do not meet the current minimum requirements.

Allow Any ROM Size for Recognition

Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's current minimum size requirements.

Allow Any Shift Register Size for Recognition

Allows the Compiler to infer shift registers of any size even if they do not meet the design's current minimum size requirements.

Allow Register Duplication

Controls whether the Compiler duplicates registers to improve design performance. When enabled, the Compiler performs optimization that creates a second copy of a register and move a portion of its fan-out to this new node. This technique improves routability and reduces the total routing wire required to route a net with many fan-outs. If you disable this option, retiming of registers is also disabled.

Note: Not available for Intel® Stratix® 10 devices.
Allow Register Merging

Controls whether the Compiler removes (merges) identical registers. When enabled, in cases where two registers generate the same logic, the Compiler may delete one register and fan-out the remaining register to the deleted register's destinations. This option is useful if you want to prevent the Compiler from removing duplicate registers that you have used deliberately. When disabled, retiming optimizations are also disabled.

Note: Not available for Intel® Stratix® 10 devices.

Allow Shift Register Merging Across Hierarchies

Allows the Compiler to take shift registers from different hierarchies of the design and put the registers in the same RAM.

Allow Synchronous Control Signals

Allows the Compiler to utilize synchronous clear and synchronous load signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but can negatively impact the fitting. This negative impact occurs because all the logic cells in a LAB share synchronous control signals.

Table 2. Advanced Synthesis Settings (2 of 13)

Option

Description

Analysis & Synthesis Message Level

Specifies the type of Analysis & Synthesis messages the Compiler display. Low displays only the most important Analysis & Synthesis messages. Medium displays most messages, but hides the detailed messages. High displays all messages.

Auto Carry Chains

Allows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers into the design. The Carry Chain Length option controls the length of the chains. When this option is off, the Compiler ignores CARRY buffers, but CARRY_SUM buffers are unaffected. The Compiler ignores the Auto Carry Chains option if you select Product Term or ROM as the setting for the Technology Mapper option.

Note: Not available for Intel® Stratix® 10 devices.

Auto Clock Enable Replacement

Allows the Compiler to locate logic that feeds a register and move the logic to the register's clock enable input port.

Auto DSP Block Replacement

Allows the Compiler to find a multiply-accumulate function or a multiply-add function that can be replaced with a DSP block.

Auto Gated Clock Conversion

Automatically converts gated clocks to use clock enable pins. Clock gating logic can contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use and overall run time. You must use the Timing Analyzer for timing analysis, and you must define all base clocks in Synopsys Design Constraints (.sdc) format.

Table 3. Advanced Synthesis Settings (3 of 13)

Option

Description

Auto Open-Drain Pins

Allows the Compiler to automatically convert a tri-state buffer with a strong low data input into the equivalent open-drain buffer.

Auto RAM Replacement

Allows the Compiler to identify sets of registers and logic that it can replace with the altsyncram or the lpm_ram_dp IP core. Turning on this option may change the functionality of the design.

Auto ROM Replacement

Allows the Compiler to identify logic that it can replace with the altsyncram or the lpm_rom IP core. Turning on this option may change the power-up state of the design.

Auto Resource Sharing

Allows the Compiler to share hardware resources among many similar, but mutually exclusive, operations in your HDL source code. If you enable this option, the Compiler merges compatible addition, subtraction, and multiplication operations. Merging operations may reduce the area your design requires. Because resource sharing introduces extra muxing and control logic on each shared resource, it may negatively impact the final fMAX of your design.

Auto Shift Register Placement

Allows the Compiler to find a group of shift registers of the same length that are replaceable with the altshift_taps IP core. The shift registers must all use the same clock and clock enable signals. The registers must not have any other secondary signals. The registers must have equally spaced taps that are at least three registers apart.

Automatic Parallel Synthesis

Option to enable/disable automatic parallel synthesis. Use this option to speed up synthesis compile time by using multiple processors when available.

Table 4. Advanced Synthesis Settings (4 of 13)

Option

Description

Block Design Naming

Specifies the naming scheme for the block design. The Compiler ignores the option if you assign the option to anything other than a design entity.

Carry Chain Length

Specifies the maximum allowable length of a chain for CARRY_SUM buffers, including those that you or the Compiler instantiate. The Compiler breaks carry chains that exceed this length into separate chains.

Note: Not available for Intel® Stratix® 10 devices.

Clock MUX Protection

Causes the multiplexers in the clock network to decompose to 2-to-1 multiplexer trees. The Compiler protects these trees from merging with, or transferring to, other logic. This option helps the Timing Analyzer to analyze clock behavior.

Create Debugging Nodes for IP Cores

Makes certain nodes (for example, important registers, pins, and state machines) visible for all the IP cores in a design. Use IP core nodes to effectively debug the IP core. This technique is effective when using the IP core with the Signal Tap Logic Analyzer. The Node Finder, using Signal Tap Logic Analyzer filters, displays all the nodes that Analysis & Synthesis makes visible. When making the debugging nodes visible, Analysis & Synthesis can change the fMAX and number of logic cells in IP cores.

DSP Block Balancing

Allows you to control the conversion of certain DSP block slices during DSP block balancing.

Table 5. Advanced Synthesis Settings (5 of 13)

Option

Description

Disable DSP Negate Inferencing

Allows you to specify whether to use the negate port on an inferred DSP block.

Disable Register Merging Across Hierarchies

Specifies whether the Compiler allows merging of registers that are in different hierarchies if their inputs are the same.

Enable State Machines Inference Allows the Compiler to infer state machines from VHDL or Verilog HDL design files. The Compiler optimizes state machines to reduce area and improve performance. If set to Off, the Compiler extracts and optimizes state machines in VHDL or Verilog HDL design files as regular logic.

Force Use of Synchronous Clear Signals

Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Enabling this option helps to reduce the total number of logic cells in the design, but can negatively impact the fitting. All the logic cells in a LAB share synchronous control signals.

HDL Message Level

Specifies the type of HDL messages you want to view, including messages that display processing errors in the HDL source code. Level1 displays only the most important HDL messages. Level2 displays most HDL messages, including warning and information based messages. Level3 displays all HDL messages, including warning and information based messages and alerts about potential design problems or lint errors.

Ignore CARRY Buffers

Ignores CARRY_SUM buffers in the design. The Compiler ignores this option if you apply the option to anything other than an individual CARRY_SUM buffer, or to a design entity containing CARRY_SUM buffers.

Ignore CASCADE Buffers

Ignores CASCADE buffers that are instantiated in the design. The Compiler ignores this option if you apply the option to anything other than an individual CASCADE buffer, or a design entity containing CASCADE buffers.

Table 6. Advanced Synthesis Settings (6 of 13)

Option

Description

Ignore GLOBAL Buffers

Ignores GLOBAL buffers in the design. The Compiler ignores this option if you apply the option to anything other than an individual GLOBAL buffer, or a design entity containing GLOBAL buffers.

Ignore LCELL Buffers

Ignores LCELL buffers in the design. The Compiler ignores this option if you apply the option to anything other than an individual LCELL buffer, or a design entity containing LCELL buffers.

Ignore Maximum Fan-Out Assignments

Directs the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity, or the whole design.

Ignore ROW GLOBAL Buffers

Ignores ROW GLOBAL buffers in the design. The Compiler ignores this option if you apply the option to anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.

Ignore SOFT Buffers

Ignores SOFT buffers in the design. The Compiler ignores this option if you apply the option to anything other than an individual SOFT buffer or a design entity containing SOFT buffers.

Table 7. Advanced Synthesis Settings (7 of 13)

Option

Description

Ignore translate_off and synthesis_off Directives

Ignores all translate_off/synthesis_off synthesis directives in Verilog HDL and VHDL design files. Use this option to disable these synthesis directives and include previously ignored code during elaboration.

Infer RAMs from Raw Logic

Infers RAM from registers and multiplexers. The Compiler initially converts some HDL patterns differing from RAM templates into logic. However, these structures function as RAM. As a result, when you enable this option, the Compiler may substitute the altsyncram IP core instance for them at a later stage. When you enable this assignment, the Compiler may use more device RAM resources and fewer LABs.

Iteration Limit for Constant Verilog Loops

Defines the iteration limit for Verilog loops with loop conditions that evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.

Iteration Limit for non-Constant Verilog Loops

Defines the iteration limit for Verilog HDL loops with loop conditions that do not evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.

Table 8. Advanced Synthesis Settings (8 of 13)

Option

Description

Limit AHDL integers to 32 Bits

Specifies whether an AHDL-based design must have a limit on integer size of 32 bits. The Compiler provides this option for backward compatibility with pre-2000.09 releases of the Intel® Quartus® Prime software. Such registers do not support integers larger than 32 bits in AHDL.

Maximum DSP Block Usage

Specifies the maximum number of DSP blocks that the DSP block balancer assumes exist in the current device for each partition. This option overrides the usual method of using the maximum number of DSP blocks the current device supports.

Maximum Number of LABs

Specifies the maximum number of LABs that Analysis & Synthesis should try to utilize for a device. This option overrides the usual method of using the maximum number of LABs the current device supports, when the value is non-negative and is less than the maximum number of LABs available on the current device.

Maximum Number of M4K/M9K/M20K/M10K Memory Blocks

Specifies the maximum number of M4K, M9K, M20K, or M10K memory blocks that the Compiler may use for a device. This option overrides the usual method of using the maximum number of M4K, M9K, M20K, or M10K memory blocks the current device supports, when the value is non-negative and is less than the maximum number of M4K, M9K, M20K, or M10K memory blocks available on the current device.

Table 9. Advanced Synthesis Settings (9 of 13)

Option

Description

Maximum Number of Registers Created from Uninferred RAMs

Specifies the maximum number of registers that Analysis & Synthesis uses for conversion of uninferred RAMs. Use this option as a project-wide option or on a specific partition by setting the assignment on the instance name of the partition root. The assignment on a partition overrides the global assignment (if any) for that particular partition. This option prevents synthesis from causing long compilations and running out of memory when many registers are used for uninferred RAMs. Instead of continuing the compilation, the Intel® Quartus® Prime software issues an error and exits.

NOT Gate Push-Back

Allows the Compiler to push an inversion (that is, a NOT gate) back through a register and implement it on that register's data input if it is necessary to implement the design. When this option is on, a register may power-up to an active-high state, and may need explicit clear during initial operation of the device. The Compiler ignores this option if you apply it to anything other than an individual register or a design entity containing registers. When you apply this option to an output pin that is directly fed by a register, the assignment automatically transfers to that register.

Number of Inverted Registers Reported in Synthesis Report

Specifies the maximum number of inverted registers that the Synthesis report displays.

Number of Protected Registers Reported in Synthesis Report Specifies the maximum number of protected registers that the Synthesis Report displays.

Number of Removed Registers Reported in Synthesis Migration Checks

Specifies the maximum number of rows that the Synthesis Migration Check report displays.

Number of Swept Nodes Reported in Synthesis Report Specifies the maximum number of swept nodes that the Synthesis Report displays. A swept node is any node which was eliminated from your design because the Compiler found the node to be unnecessary.
Number of Rows Reported in Synthesis Report

Specifies the maximum number of rows that the Synthesis report displays.

Note: Not available for Intel® Stratix® 10 devices.

Optimization Technique

Specifies an overall optimization goal for Analysis & Synthesis. The Compiler can maximize synthesis processing for performance, minimize logic usage, or balance high performance with minimal logic usage.

Table 10. Advanced Synthesis Settings (10 of 13)

Option

Description

Perform WYSIWYG Primitive Resynthesis

Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the setting specified in the Optimization Technique logic option.

Power-Up Don't Care

Causes registers that do not have a Power-Up Level logic option setting to power-up with a do not care logic level (X). When the Power-Up Don't Care option is on, the Compiler determines when it is beneficial to change the power-up level of a register to minimize the area of the design. The Compiler maintains a power-up state of zero, unless there is an immediate area advantage.

Power Optimization During Synthesis

Controls the power-driven compilation setting of Analysis & Synthesis. This option determines how aggressively Analysis & Synthesis optimizes the design for power. When this option is Off, the Compiler does not perform any power optimizations. Normal compilation performs power optimizations provided that they are not expected to reduce design performance. Extra effort performs additional power optimizations which may reduce design performance.

Table 11. Advanced Synthesis Settings (11 of 13)

Option

Description

Remove Duplicate Registers

Removes a register if it is identical to another register. If two registers generate the same logic, the Compiler deletes the duplicate. The first instance fans-out to the duplicates destinations. Also, if the deleted register contains different logic option assignments, the Compiler ignores the options. This option is useful if you want to prevent the Compiler from removing intentionally duplicate registers. The Compiler ignores this option if you apply it to anything other than an individual register or a design entity containing registers.

Remove Redundant Logic Cells

Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes a circuit for area and speed. The Compiler ignores this option if you apply it to anything other than a design entity.

Report Connectivity Checks

Specifies whether the Synthesis report includes reports under the Connectivity Checks folder.

Note: Not available for Intel® Stratix® 10 devices.

Report Parameter Settings

Specifies whether the Synthesis report includes the reports in the Parameter Settings by Entity Instance folder.

Report Source Assignments

Specifies whether the Synthesis report includes reports in the Source Assignments folder.

Table 12. Advanced Synthesis Settings (12 of 13)

Option

Description

Resource Aware Inference for Block RAM

Specifies whether RAM, ROM, and shift-register inference should take the design and device resources into account.

Restructure Multiplexers

Reduces the number of logic elements synthesis requires to implement multiplexers in a design. This option is useful if your design contains buses of fragmented multiplexers. This option repacks multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced number of logic elements:
  • On—minimizes your design area, but may negatively affect design clock speed (fMAX).
  • Off—disables multiplexer restructuring; it does not decrease logic element usage and does not affect design clock speed (fMAX).
  • Auto—allows the Intel® Quartus® Prime software to determine whether multiplexer restructuring should be enabled. The Auto setting decreases logic element usage, but may negatively affect design clock speed (fMAX).

SDC Constraint Protection

Verifies.sdc constraints in register merging. This option helps to maintain the validity of .sdc constraints through compilation.

Safe State Machine

Directs the Compiler to implement state machines that can recover from an illegal state.

Shift Register Replacement – Allow Asynchronous Clear Signal

Allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps IP core. The shift registers must all use the same aclr signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart. To use this option, you must turn on the Auto Shift Register Replacement logic option.

Table 13. Advanced Synthesis Settings (13 of 13)

Option

Description

State Machine Processing

Specifies the processing style the Compiler uses to process a state machine. You can use your own User-Encoded style, or select One-Hot, Minimal Bits, Gray, Johnson, Sequential, or Auto (Compiler-selected) encoding.

Strict RAM Replacement

When this option is On, the Compiler replace RAM only if the hardware matches the design exactly.

Synchronization Register Chain Length

Specifies the maximum number of registers in a row that the Compiler considers as a synchronization chain. Synchronization chains are sequences of registers with the same clock and no fan-out in between, such that the first register is fed by a pin, or by logic in another clock domain. The Compiler considers these registers for metastability analysis. The Compiler prevents optimizations of these registers, such as retiming. When gate-level retiming is enabled, the Compiler does not remove these registers. The default length is set to two.

Synthesis Effort

Controls the synthesis trade-off between compilation speed, performance, and area. The default is Auto. You can select Fast for faster compilation speed at the cost of performance and area.

Synthesis Migration Check for Stratix 10 Enables synthesis checks on Intel® Arria® 10 to Intel® Stratix® 10 design migration.

Timing-Driven Synthesis

Allows synthesis to use timing information to better optimize the design. The Timing-Driven Synthesis logic option impacts the following Optimization Technique options:

  • Optimization Technique Speed—optimizes timing-critical portions of your design for performance at the cost of increasing area (logic and register utilization)
  • Optimization Technique Balanced—also optimizes the timing-critical portions of your design for performance, but the option allows only limited area increase
  • Optimization Technique Area—optimizes your design only for area