The Acceleration Stack for Intel® Xeon® CPU with FPGAs is a robust collection of software, firmware, and tools designed and distributed by Intel to make it easier to develop and deploy Intel® FPGAs for workload optimization in the data center. The Acceleration Stack for Intel® Xeon® CPU with FPGAs provides optimized and simplified hardware interfaces and software application programming interfaces (APIs), saving the developer time so they can focus on the unique value-add of their solution.

The Intel® Acceleration Stack provides multiple benefits to design engineers:

  • Saves developer time to focus on unique value-add of their solution
  • Enables code-reuse across multiple Intel FPGA form-factor products
  • Establishes the world's first common developer interface for Intel FPGA data center products
  • Offers optimized and simplified hardware and software APIs provided by Intel

Open Programmable Acceleration Engine (OPAE) Technology

Open Programmable Acceleration Engine (OPAE) technology is a software programming layer that provides a consistent API across FPGA product generations and platforms. It is designed for minimal software overhead and latency, while providing an abstraction for hardware specific FPGA resource details. To foster an open ecosystem and encourage the use of FPGA acceleration for data center workloads, Intel has open sourced the technology for the industry and developer community.

Features of Open Programmable Acceleration Engine technology:
  • Lightweight user-space library (libfpga)
  • License: FPGA API (BSD), FPGA driver (GPLv2)
    • FPGA driver being upstreamed into Linux* kernel
  • Supports both virtual machines and bare metal platforms
  • Faster development and debugging of accelerator functions with the included AFU Simulation Environment (ASE)
  • Includes guides, command-line utilities, and sample code

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