FPGA designers can now develop accelerator functions using any Hardware Description Language (HDL) (e.g. Verilog/VHDL). A great way to get started is to simply select a platform and use the provided FPGA Interface Manager to seemlessly integrate your accelerator function with the software framework and applications on Intel® Xeon® CPUs.
Accelerator functions can be developed using a high-level design language (e.g. OpenCL™) by simply selecting a platform and using the provided OpenCL board support package (BSP) to seamlessly integrate the developed accelerator function with software framework and applications on Intel® Xeon® CPUs.
Software developers can make use of the Open Programmable Acceleration Engine software programming layer to develop libraries, frameworks, and applications that call accelerator functions implemented in FPGA hardware.
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