BMS Reference Design

 Collaborating with the University of Pisa, Altera has released its first Battery Management System (BMS) reference design and application note. This reference design demonstrates the FPGA's complex parallel computing capability to estimate the State Of Charge (SOC) with a dual extended Kalman filter algorithm on a MAX® 10 FPGA in a system-in-loop model. It opens new possibilities to develop smarter BMSs to allow online SOC measurement methodology by off-loading complex algorithms to programmable hardware, freeing remaining CPU resources for other important tasks.

Download reference design and application note >>

Make Your Battery Management System Even Smarter

The battery is the most expensive component in an electric vehicle. Its cost has a direct impact on the value of the vehicle because driving mileage is determined primarily by battery capacity. The battery needs to be managed efficiently to make optimum use of the energy in its cells, and to prevent electrical damage to the cells, which shortens battery cycle life. 

Low-cost microcontroller units (MCUs) are sufficient for basic control functions, but the increasing number of battery cell and functional safety requirements drives the need for better control methods and architecture to meet system costs and stringent safety criteria. FPGAs are ideal solution to these design challenges.

FPGAs offer:

  • Performance improvement: Run more advanced algorithms faster and parallel to improve performance
  • System cost reduction: Integration of several components, monitor more modules/cells with multiple serial interfaces
  • Scalability: Support latest advanced interface protocol which is not on current MCUs
  • Safety: Implement hardware fail-safe logic

 

MAX 10 FPGAs enable you to implement unique features in your battery management system:

  • System power control: MAX 10 FPGAs offer a sleep mode by keeping state and wake-up within 1 msec
  • Dual boot image: Change operation mode per use case with a dual-boot image (i.e., driving vs. charging mode)

Two Architectural Approaches: Master or Companion

Altera supports two different architectural approaches to enhance your system while maximizing the benefit of programmable logic.

  • Use the MAX 10 FPGA as the system master with the embedded Nios® II soft processor core, which is a royalty-free, compact size real time processor. You can visit here and download white paper to learn the benefits of using MAX 10 FPGAs with the Nios II processor.
  • Maximize performance and flexibility without major architectural changes. A MAX 10 FPGA can be a great companion solution to off-load complex algorithm processing from an existing CPU. For example, a Kalman filter can greatly improve the accuracy of the SOC in a BMS. You can implement it in a MAX 10 FPGA as a hardware accelerator to improve system performance without changing the main processor. 

White Paper: Improving Battery Management System Performance and Cost

For more details about the BMS architecture and FPGA value proposition, download our white paper.

Download BMS White Paper >>