How to Improve Your Head Unit Design with FPGAs

How can you get more design flexibility in your infotainment system’s head unit? Application processors (systems on a chip) with high-performance graphics processing units (GPUs), CPUs, and peripherals can be upgraded in software, but may not be able to keep up with changing interfaces and system variations. By adding an FPGA to your design, you get the flexibility to quickly change the I/O configuration, even in the last phase of development, helping you meet different OEM and interface requirements.

Head Unit Block Diagram

USB 3.0 Chip-to-Chip Links in Infotainment Applications

Joe describes how an embedded USB3.0 Interface face can be used to connect a Applications processor SoC can be connected to a Companion FPGA for IO Expansion, Video MUXing and pre-processing enhancements for a Head Unit application.

The USB3.0 interface provides a fast (5 Gbps), Full Duplex interface over just four pins using transceivers in the Cyclone V GT FPGA.

This example features SLS's Embedded USB3.0 Device Controller IP.

Take a look!

 

Our FPGAs can help you:

  • Eliminate interface constraints to widen your choice of ASSPs
  • Implement the latest interface intellectual property (IP) as a bridge function to re-use existing ASSPs, lowering cost and design time without sacrificing features
  • Scale your design to adapt to multiple sizes and resolutions of LCD modules
  • Bridge your ASSP to the latest interface with our selection of IP from Altera and partners
  • Design front-end and back-end processing systems using our video input/output selector to support multiple cameras, monitors, and other applications with limited image processing capability, as shown in Figure 1

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