Figure 1. Typical LCD TV Interface Block Diagram

Flat panel displays (LCDs, plasma display panels, plasma low-profile, and liquid crystal on silicon) and video projectors receive, decode, and display digital video streams from a variety of sources. As prices of flat panel TVs decrease, they are becoming more common in consumer households.

The heart of the LCD HDTV is its image processing and timing control block (shown in Figure 1). The image processing block typically includes functions such as scan rate converter, frame rate converter, color decoder, motion detection, scalar, and de-interlacing.

The color response time of an HDTV LCD display is slower than a conventional display, and depends on the color content. This challenges the development of image-processing algorithms when the additional requirement to eliminate any viewing artifact is factored in. FPGA design flexibility offers a significant advantage, allowing you to redesign the algorithm within the device without having to reprogram it.

Once the data has been processed, the video board interfaces to the LCD column and row drivers through a LVDS bus or a Reduced Swing Differential Signaling (RSDS) bus running up to 400 Mbps.

IP and Development Kits Offered by Altera and Partners

Altera offers a broad portfolio of intellectual property (IP) cores for display applications. The IP cores include, embedded processors, video and Image processing functions, standard interfaces, and peripherals. You can add proprietary logic to this wide portfolio of IP cores to develop unique solutions in a timely fashion. You can obtain these IP cores either directly from Altera or from third-party IP partners. All the IP cores are thoroughly tested and optimized for Altera® products. Some of the video display related IP from Altera include:

Altera and its partners also offer development kits to accelerate the flat panel display design process. These kits based on Altera’s FPGAs allow display designers and ASSP vendors to add next-generation picture enhancement features to their products as market demands evolve, rather than being tied to lengthy ASIC development cycles.

Low-Cost Programmable Solutions for Displays and Projectors

Altera’s low-cost Cyclone III and MAX® II devices provide the most cost-effective programmable solution for A/V processing, making these devices ideal for digital video applications. Cyclone series FPGAs and MAX series CPLDs also contain system functions that complement available ASSPs, such as OSD and timing display.

Cyclone III FPGAs are built on a 65-nm, low-power process technology. The Cyclone III family includes eight devices ranging from 5K to 120K logic elements (LEs) and up to 534 user I/O pins. Cyclone III FPGAs offer up to 4 Mbits of embedded memory, 288 embedded 18 x 18 multipliers, dedicated external memory interface circuitry, and phase-locked loops (PLLs) making them ideal for high-end video and image processing functions. Additional features include high-speed differential signal I/O capabilities to enable LVDS and RSDS interfaces used in flat panel displays.

Altera’s MAX devices are the industry’s most successful and widely used CPLD solutions. Altera’s latest CPLDs, MAX II devices, are designed for low-cost and low-power applications. The non-volatile and low-cost features of the MAX II devices make them ideal for display functions such as address decoding, system timing, and system bug fixes.

Interfaces Support in Cyclone FPGAs