Motors and drives power countless industrial processes in production, assembly, packaging, robotics, computer numerical control (CNC), machine tools, pumps, and industrial fans. These motor-driven systems account for more than two-thirds of industrial energy consumption, making their efficient operations vital to factory profits.
Efficient Motor Control Designs with Intel® FPGAs and SoCs
Designing motor control and motion control systems with Intel® FPGAs and SoCs can result in significant reduction in overall cost of ownership through:
- System integration: Lower bill of materials (BOM), power consumptio,n and reliability challenges by integrating industrial networking, functional safety, encoder, and power stage interfaces and digital signal processing (DSP) control algorithms in a single device.
- Scalable performance: Use a single scalable platform across entire product lines. Achieve higher performance with faster and more advanced control loops.
- Functional safety: Reduce compliance time and effort. Intel is the first FPGA supplier to obtain qualification of our devices and tools under the Machinery Directive safety standard IEC 61508.
Figure 1. "Drive-on-a-Chip": Intel MAX 10 FPGA, Cyclone V FPGA or Cyclone V SoC with High-Performance Processors, Motor Control Algorithm, I/O Logic, Industrial Ethernet Protocols, and Safety Elements
Unlike traditional motor control drive designs based on ASICs, ASSPs, microcontrollers, and DSP devices, a drive system based on a single Intel FPGA platform, as shown in Figure 1, provides a scalable platform that supports diverse drive needs.
The Intel Motor Control Development Framework enables you to easily create integrated, high-performance drive-on-a-chip motor control designs for Intel Cyclone FPGAs and SoCs. The framework comprises reference designs, software libraries, intellectual property (IP) cores, and a portfolio of motor control hardware platforms supporting the development of motor control systems in a single FPGA.
The Motor Control Development Framework seamlessly integrates system-level design and software development tools for embedded Nios II and ARM processors, allowing you to extend and customize the motor control reference designs to meet your own application needs. Our Cyclone® FPGAs, with high-performance fixed- and floating-point DSP functionality and Nios II soft processor support, offer a scalable and flexible platform for integration of cost-effective single- and multiaxis drives on a single FPGA.
Figure 1. Drive-on-a-Chip Motor Control Reference Design (Multiaxis)
Intel provides a suite of single-and multi-axis drive-on-a-chip reference designs that include a complete FOC IP subsystem integrated with key motor control and interface IP, and system software running on the integrated processor.
Drive-on-a-Chip Reference Design
The drive-on-a-chip reference design is a fully integrated single- and multiaxis motor control system implementation targeting Cyclone FPGAs and Cyclone SoCs. The reference design, as shown in Figure 1, implements a software-configurable field-oriented-control (FOC) algorithm for concurrent control of up to four permanent magnet synchronous motors (PMSM) integrated with key motor control interface IP.
The motor control reference design includes the following features:
- Complete software system running on either the dual ARM Cortex-A9 hard processor system or a Nios II processor, performing high-level control and configuration (in addition to closing of motor position and speed loops)
- Software-only and FPGA-accelerated FOC implementations interfacing position and speed loops in software with an ultra-low latency, high-performance current control loop in the FPGA as a DSP coprocessor
- Optimized and software-configurable FOC IP subsystem with support for both fixed- and floating-point precision implementations
- Integrates key motor control functions, such as space vector pulse-width modulation (PWM), Sigma-Delta ADC interface and filter logic, and position feedback encoder interfaces in the FPGA, all under control of software
The following hardware platforms support the Intel motor control reference designs:
Figure 3. Tandem Motion Power
The Intel Cyclone V SoC FPGA Development Kit, SoCKit Development Kit from Terasic and the Intel MAX10 FPGA Development Kit support the drive-on-a-chip motor control reference design. Designs running on the FPGA host boards connect to the dual axis Tandem Motion Power 48 V Board over a high-speed mezzanine card (HSMC) interface.
The Tandem Motion Power 48 Board was developed in conjunction with D3 Engineering and is available from Terasic.
The FalconEye motor control development kits are no longer supported by the Drive On Chip motor control reference designs