Differentiate Your Drive

Motors and drives power countless industrial processes in production, assembly, packaging, robotics, computer numerical control (CNC), machine tools, pumps, and industrial fans. These motor-driven systems account for more than two-thirds of industrial energy consumption, making their efficient operations vital to factory profits.

Efficient Motor Control Designs with Intel® FPGAs and SoCs

Designing motor control and motion control systems with Intel® FPGAs and SoCs can result in significant reduction in overall cost of ownership through:

  • System integration: Lower bill of materials (BOM), power consumptio,n and reliability challenges by integrating industrial networking, functional safety, encoder, and power stage interfaces and DSP control algorithms in a single device.
  • Scalable performance: Use a single scalable platform across entire product lines. Achieve higher performance with faster and more advanced control loops.
  • Functional safety: Reduce compliance time and effort. Intel® is the first FPGA supplier to obtain qualification of our devices and tools under the Machinery Directive safety standard IEC 61508.

Unlike traditional motor control drive designs based on ASICs, ASSPs, microcontrollers, and DSP devices, a drive system based on a single Intel® FPGA platform, as shown in Figure 1, provides a scalable platform that supports diverse drive needs.

 

Figure 1. "Drive-on-a-Chip": MAX® 10 FPGA, Cyclone® V FPGA or Cyclone V SoC with High-Performance Processors, Motor Control Algorithm, I/O Logic, Industrial Ethernet Protocols, and Safety Elements

Simplify your motor control design with flexible design entry methodologies from Intel®. Intel® motor control design flows are flexible to suit the particular needs of Embedded Software engineers, System/Integration engineers, Matlab/Simulink algorith developers and FPGA hardware engineers. Use software based design flows to target the integrated ARM Cortex A9 hard processor systems or Nios soft processors in Intel® FPGAs and SoCs.

Use Simulink and Embedded Coder from MathWorks to generate C/C++ code for Intel® Cyclone V SoCs. When used in combination with Intel®SoC support from HDL Coder, this solution can be utilized in a hardware/software workflow spanning simulation, prototyping, verification, and implementation on Intel® SoCs. For more information, visit www.mathworks.com/altera-soc.

The Intel® Motor Control Development Framework enables you to easily create integrated, high-performance drive-on-a-chip motor control designs for Intel® Cyclone® FPGAs and SoCs. The framework comprises reference designs, software libraries, intellectual property (IP) cores, and a portfolio of motor control hardware platforms supporting the development of motor control systems in a single FPGA.

The Motor Control Development Framework seamlessly integrates system-level design and software development tools for embedded Nios® II and ARM® processors, allowing you to extend and customize the motor control reference designs to meet your own application needs. Our Cyclone FPGAs, with high-performance fixed- and floating-point DSP functionality and Nios II soft processor support, offer a scalable and flexible platform for integration of cost-effective single- and multiaxis drives on a single FPGA.

Intel® provides a suite of single-and multi-axis drive-on-a-chip reference designs that include a complete FOC IP subsystem integrated with key motor control and interface IP, and system software running on the integrated processor.

Drive-on-a-Chip Reference Design

The drive-on-a-chip reference design is a fully integrated single- and multiaxis motor control system implementation targeting Cyclone® FPGAs and Cyclone SoCs. The reference design, as shown in Figure 1, implements a software-configurable field-oriented-control (FOC) algorithm for concurrent control of up to four permanent magnet synchronous motors (PMSM) integrated with key motor control interface intellectual property (IP).

Figure 1. Drive-on-a-Chip Motor Control Reference Design (Multiaxis)

 

The motor control reference design includes the following features:

  • Complete software system running on either the dual ARM® Cortex™-A9 hard processor system or a Nios® II processor, performing high-level control and configuration (in addition to closing of motor position and speed loops)
  • Software-only and FPGA-accelerated FOC implementations interfacing position and speed loops in software with an ultra-low latency, high-performance current control loop in the FPGA as a DSP coprocessor
  • Optimized and software-configurable FOC IP subsystem with support for both fixed- and floating-point precision implementations
  • Integrates key motor control functions, such as space vector pulse-width modulation (PWM), Sigma-Delta ADC interface and filter logic, and position feedback encoder interfaces in the FPGA, all under control of software

 

Motor Control Reference Design

The following hardware platforms support the Intel® motor control reference designs:

  Kit / Board Description Vendor
FPGA Host Control Boards Altera Cyclone IV E Industrial Networking Kit Terasic
Altera Cyclone V E FPGA Development Kit Intel®
Altera Cyclone V SoC Development Kit Intel®
Motor Control Power Board Options (Connect to FPGA Control Boards over HSMC) Single-Axis Falcon Eye-II HSMC Power Board Devboards.de
Multi-Axis Motor Control Power Board D3 Engineering

The Cyclone IV-based Industrial Networking Kit (INK) from Terasic and the Intel® Cyclone V E FPGA and Cyclone V SoC Development Kits support the drive-on-a-chip motor control reference design. Designs running on the FPGA host boards connect to the single-axis HSMC-Falconeye and multiaxis motor control power boards over a high-speed mezzanine card (HSMC) interface. The motor control design is also available in a single-axis version for development on the EBV Elektronik FalconEye and Falconeye-II motor control development kits, also available from devboards.de

Figure 2. Single-Axis Motor Control System

Figure 3. Multiaxis Motor Control System