High-Definition Wide Dynamic Range Video Surveillance Chipset
The industry's first high-definition (HD) wide dynamic range (WDR) video surveillance chipset from Altera simplifies the development of video surveillance camera systems. It provides a single vendor source for the intellectual property (IP) and FPGA.
Our exclusive chipset combines an Altera® Cyclone® IV E FPGA with a security chip that supports Apical's HD WDR full image signal processing (ISP) pipeline IP and AltaSens' 1080p60 A3372E3-4T image sensor. We are streamlining access to Apical's IP and reducing your risk by giving you a complete sensor processing solution. To learn more, contact your local Altera sales representative.
No other ASSP or digital signal processing (DSP) platform offers a comprehensive pipeline that incorporates WDR technology using a 1080p60 sensor and data path. And FPGAs are the only devices that can handle the large bandwidth of data from 1080p and 720p WDR CMOS sensors.
Image Sensor Processing Pipeline Challenge
WDR sensors output up to 20 bits of raw image data, but lack an ISP, making it a challenge to connect them to standard ASSP or DSP devices.
Figure 1 shows two photographs of a street scene comparing what the output would look like from a standard camera (on the left) versus a camera with a WDR image sensor using appropriate image processing (on the right). Compared to the unprocessed left image in Figure 2, the right image shows how the high-performance ISP IP core allows the maximum detail to be extracted from a high-contrast scene. In particular, the example reveals the dark areas without corresponding overexposure in the bright areas.
Figure 1. Standard Sensor vs. WDR Sensor Output Image
Images courtesy of Apical Ltd
Although WDR sensors support high-quality resolution and higher frame rates, it requires more computing power to process these images such as pixel-by-pixel correction, local toning, and white balancing. This poses a challenge for off-the-shelf DSPs and even some ASSPs because CMOS WDR sensors have no on-chip image pipeline processing and output the image data in RAW/Bayer format at up to 20 bits per pixel. The large amount of raw data coming from the sensor can be computed as:
- 20 bits/pixel x (1280 x 720) pixels/frame x 60 frames/s = >1 gigabits per second (Gbps)
This large amount of data makes it difficult to connect next-generation WDR sensors to ASSPs commonly used in surveillance solutions.
Altera Video Surveillance Solution
Using Altera's Cyclone III or Cyclone IV FPGAs, along with our video surveillance camera reference solution, the FPGA can be used to connect directly to the image sensor, implement the full ISP, and connect to any encoder or PHY device. In addition, the FPGA can be optionally used to perform H.264 encoding and to create a full Internet protocol camera pipeline on one chip – all without the need for an external DSP device or ASSP.
Altera FPGAs are the ideal choice for efficient processing of HD WDR sensor data. Together with Altera's partner, Apical, a leader in image processing IP, this HD WDR sensor interface solution offers an ISP (Figure 3) with the following functions:
- Hot pixel removal and noise reduction (spatial and temporal IP cores are available)
- Advanced per pixel tone mapping (Apical's patented Iridix IP core)
- Advanced demosaic and color correction
Figure 2. Block Diagram of Apical's ISP
Streamlined Image Sensor Pipeline IP Delivery
The Altera, Apical, and AltaSens solution provides a low-risk, low-cost method for camera manufacturers to implement the ISP in a simple chipset. This exclusive solution incorporates:
- Altera Cyclone IV E FPGA with a pre-programmed security device that supports Apical's HD WDR full image signal processing (ISP) pipeline IP
- AltaSens' 1080p60 A3372E3-4T image sensor technology
This unique solution streamlines access to Apical's IP and mitigates the customer risk by providing a complete sensor interface solution.
The chipset simplifies the development of a video surveillance camera system by providing a single vendor source for the IP and the FPGA. You no longer have to purchase the IP from a separate vendor and pay extra licensing fees or non-recurring engineering (NRE) charges. The price of the chipset is all you pay.
Your local Altera sales representative can assist you with the easy download of Apical's IP, registration for an evaluation license online, and evaluation of your system before purchasing the chipset. After evaluation, you can obtain and license the IP online and incorporate the IP into your Quartus® Prime FPGA design. This ready-made, yet flexible chipset decreases development time and adds flexibility to the camera design. Because of the FPGA's flexibility, you can customize the device with your specific features to further differentiate your product from competitors.