Optimal control of new or upgraded smart grids require end-to-end communications and efficient power networks, especially in transmission and distribution (T&D) substations. To support automation, the equipment needs to monitor, control, and secure the grid in real time for more efficient management of peak demand loads. Intel® FPGA technologies play pivotal roles across the complex smart grid ecosystem.

Typical Substation Automation Architecture

Across substation and utility automation applications, IEC 61850 over Ethernet with IEC 62439-3 Clause 4 Parallel Redundancy Protocol (PRP) and Clause 5 High-Availability Seamless Redundancy (HSR) standards are fast becoming the backbone of high-availability networks in smart grid systems. Designers will face some tough challenges when dealing with substation equipment that must support mission-critical systems in real time and long life cycles that place demands on reliability, upgradability, and interchangeability.

The real-time switch requirements in a redundant network are ideal for implementing in FPGAs. Our low-cost Cyclone® V FPGAs and Cyclone® V SoCs meet the performance requirements of Gbps Ethernet traffic with PRP/HSR redundancy and evolving PRP/HSR standards.

No-Hassle PRP/HSR Ethernet Switch On FPGA

To make it easier for you to implement your smart grid design, we teamed with Flexibilis, a leading networking equipment and intellectual property (IP) provider. The Flexibilis Redundant Switch (FRS) is a GbE switch that supports both PRP and HSR protocol standards. The combination of our FPGA with the FRS IP provides an easy and cost-effective way for you to develop your PRP/HSR switch with:

  • No license negotiation
  • No up-front licensing costs
  • No per-unit royalty reporting

Flexibilis Redundant Switch for Cyclone® V FPGA and Cyclone® V SoC

Key features of the FRS IP:

  • Scalable from three to eight ports on our Cyclone® IV, Cyclone® V, and Cyclone® V SoC devices
  • Full-duplex 1000 Mbps (GMII1) and 10/100 Mbps (MII2) on all ports
  • Wire-speed packet forwarding
  • Non-blocking operations
  • Reliable store-and-forward operation with data integrity checking
  • HSR redundancy box (RedBox), HSR end-node, and HSR quadruple port device (QuadBox); PRP RedBox and doubly attached nodes for PRP (DANP)
  • Compatible with IEEE 1588 Precision Time Protocol (PTP) transparent clock

Three Steps to Starting Your Design

  1. Request the IP and review the technical documentation.
  2. Download the reference design.
  3. When you are ready to go into production, purchase your FPGA plus a low-cost security CPLD through your local Intel® FPGA sales representative.

1Gigabit media independent interface
2 Media independent interface