In electronic warfare systems, key drivers for continuous enhancements are electronic counter-counter-measures (ECCM), stealth technologies, closely interlinked smart sensor networks, and intelligent guided weapons. These systems must be able to rapidly analyze and respond to multiple threats in very short time frames. In attempting to find target signatures in broadband noise, architects are seeking to perform complex processing such as fast Fourier transforms (FFTs), Cholesky decomposition, and matrix multiplication. Multiple software-generated waveforms are then transmitted to provide false targets, while powerful wideband signals provide overall cover. These shifting tactical responses require agile, high-performance processing. The entire system frequently resides in an airborne platform and must meet strict requirements for heat dissipation along with size, weight, power, and cost (SWaP-C) constraints.
A typical system design, shown in Figure 1, uses a channelizer and inverse-channelizer to process high-bandwidth input signals. The number of channels are flexible so system designers can allocate hardware resources versus system performance as needed.
Figure 1. Electronic Warfare Jammer System Architecture
FPGAs offer an ideal solution to these performance requirements in the critical high-speed processing-intensive paths, a typical electronic warfare system with different electronic attack (EA) techniques.
Floating-Point Performance at Minimum Power
Electronic warfare designers can optimize digital signal processing (DSP) resources while still meeting SWaP-C constraints at the highest energy efficiency (GFLOPS/Watt) in any FPGA device across the industry. Using Altera’s floating-point tools (OpenCL, DSP Builder, MegaCores, and MegaFunctions), DSP pipelines can be implemented quickly and optimized to up to 1.5 TFLOPs on an Arria 10® FPGA and up to 10 TFLOPs on Stratix 10 FPGAs.
Sensor and Backplane Interface
Stratix V FPGAs have transceivers with speeds to 28 Gbps. A complete portfolio of transceivers is available to support a wide variety of backplane interfaces at minimum latency.
Shorter Time to Market and Less Engineering Risk
Altera has a complete set of intellectual property (IP) cores, reference designs, development kits, and system-level design tools. For specific electronic warfare reference designs and support, please contact us at firstname.lastname@example.org.
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