Military Digital Signal Processing

Radar, secure communications, and electronic warfare all have at their roots in high-performance digital signal processing (DSP) chains with a performance range from one GFLOPS to ten TFLOPS. Achieving this level of performance, while still maintaining reasonable size, weight, and power (SWaP), is a challenge.

System architects often develop their concepts and models in MathWorks's MATLAB, then a separate team quantizes the mathematical models for execution in fixed-point-capable hardware. This quantization step often introduces deviation from original model and suffers from possible dynamic range constraints or other system issues.

Arria 10 and Stratix 10 FPGAs will offer the industry highest GFLOPS/Watt ratio to help maintain SWaP. An IEEE 754- compliant floating-point processing chain can significantly reduce the processing burden, reducing the need for repeated normalization, and consequently increase the hardware efficiency. The floating-point capability of FPGAs can eliminate the quantization step between MATLAB and hardware implementation while maintaining the designer's original system specification. Arria 10 and Stratix 10 FPGAs will offer up to 1.5 & 10 TFLOPs respectively.

Figure 1 highlight some of the high-performance DSP capabilities in Stratix® V FPGAs. These include integrated coefficient registers, hard pre-adders, and three multiplier modes for flexibility. The DSP architecture along with DSP Builder Advanced Blockset with fused data-path flow saves memory and routing resources while enabling designers to choose the precise blend of precision, utilization, and power.

Figure 1. 18-bit and High-Precision Modes



Altera offers solutions, reference designs, and technical support to address military DSP applications. For more details, please contact us at

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