In today's modern radar systems, Active Electronically Scanned Array (AESA) is the most popular architecture. Going forward, next-generation radar architectures such as digital phased array and synthetic aperture radar (SAR) with ground moving target indicator (GMTI) will be the emerging technology. To achieve this, parameters such as high-performance data processing, ultra-wide bandwidth, high dynamic range, and adaptive systems needed for diverse mission requirements are some of the most common challenges to system designers.
An FPGA is an ideal, and in some cases necessary, solution in addressing these challenges. In the AESA architecture shown in Figure 1, one can easily identify several stages where an FPGA is necessary and where an FPGA provides a significant processing advantage.
Using floating-point technology with Intel® Stratix® FPGAs with variable-precision digital signal processing (DSP) allows the designer to define the needed precision for each stage of the design. Logic and DSP resources are used efficiently while reducing power consumption.
Figure 1. AESA Architecture
The 28 nm Stratix V FPGAs address the unique design requirements of radar and advanced sensor technologies. With 825 Gbps full-duplex serial transceiver bandwidth, large DSP counts, excellent signal integrity, highly scalable embedded processing blocks, and logic density leadership up to 950K logic elements (LEs), Stratix V FPGAs offer true system-on-chip (SoC) possibilities for military radar and sensor designs.
With next-generation Intel Arria® 10 and Stratix 10 devices, the large DSP counts will be supplemented with the addition of hard floating-point IEEE-754 single precision DSP blocks. This will allow up to 1.5 TeraFLOPs in Arria 10 FPGAs and up to 10 TeraFLOPs in Stratix 10 FPGAs. Designers can infer these blocks using the OpenCL™ flow, DSP Builder for Intel FPGAs, and other Intel FPGA intellectual property (IP) blocks.
To enable shorter development time, Intel complements our silicon solutions with IP cores, reference designs, development kits, and system-level design tools. For specific radar reference designs and radar application support, please contact us at firstname.lastname@example.org.
|Joint Webcasts with Mathworks||Using Mathworks MATLAB and Simulink to solve floating point challenges in developing radar applications|
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|"Radar Processing: FPGAs or GPUs?"||
While general-purpose graphics processing units (GP-GPUs) offer high rates of peak floating-point operations per second (FLOPs), FPGAs now offer competing levels of floating-point processing. Moreover, Intel FPGAs now support OpenCL™, a leading programming language used with GPUs.