Communication test and monitoring equipment consists of various products in the wireline, wireless, optical, and telecommunication market segments. These products include network/protocol analyzers, spectrum analyzers, bit-error rate testers (BERTs), voice over Internet protocol (VoIP) testers, SONET/SDH testers, and more.
Designing communication test products presents a two-fold challenge:
- The need to support a variety of standards such as PCI Express® (PCIe®) and 10 Gigabit Ethernet (10GbE) well ahead of equipment manufacturers
- The constant pressure to upgrade products that support emerging standards, new features, and new functionality
As a result, designers need programmable solutions that provide the flexibility to upgrade and prolong the life of the tester equipment. Programmability is both a business and design requirement, making FPGAs the ideal solution for these applications.
Figure 1 illustrates the use of Intel® FPGAs and Intel® FPGA Intellectual Property (IP) functions in a multiport network/protocol analyzer. There are three key functional blocks in a typical tester line card: a generator, a framer/media acess control (MAC), and an analyzer. The generator generates the test pattern, which is sent to the framer for framing and then over to the device under test (DUT). Once the data comes back from the DUT, the framer sends the data to the analyzer for bit-error rate (BER) testing, histogram, and various other test procedures.
Key System Architecture Variables
- Number of ports per line card
- Power (total power dissipation per board: maximum 50 – 60 W)
- Multiple ports with varying network protocols (Ethernet, GbE, optical, etc.)
- Software/hardware partitioning (Layers 1 – 7)
The feature-rich architecture of the Stratix®, Arria®, and Cyclone® series FPGAs provides an excellent solution for communication tester equipment production needs. These programmable device families give system designers flexibility, performance, integration, and design resources that are not available in any other device solution. These devices along with Intel’s extensive portfolio of IP cores give designers industry-leading development solutions for the next generation of communication tester equipment.
Stratix series FPGAs use a high-performance architecture that accelerates block-based designs for maximum system performance. Stratix devices include up to 5.5M quivalent logic elements (LEs), up to 229 Mb of embedded memory, high-performance, variable-precision digital signal processing (DSP) blocks with up to 11,520 18x19 high-performance multipliers, and flexible I/Os for most popular interface standards.
Stratix series devices also include transceivers capable of data rates up to 30 Gbps, as well as up to 144 full-duplex transceiver channels supporting data rates up to 30 Gbps, with the accuracy required for multiple serial protocols such as PCIe 1.1, 2.0, and 3.0. The inclusion of integrated transceivers in some family members provides a solution that is efficient in both cost and board space for communication tester products. Built on the Stratix architecture, Stratix devices include the embedded memory and LE resources needed for input and output data processing functions, such as framing, BER testing, and clock signal synchronization.
Arria® FPGA series include unique innovations such as an embedded dual-core ARM® CortexTM-A9 MPCoreTM processor. This hard processor system (HPS) includes a rich set of hardened peripherals, the lowest power transceivers at 10.3125 Gbps and 17.4 Gbps, hardened memory interfaces, and a power-optimized core architecture that comprises redesigned adaptive logic modules (ALMs), variable-precision DSP blocks, distributed memory blocks, and fractional clock synthesis phase-locked loops (PLLs).
Low-cost Cyclone series FPGAs are a precise fit for applications that need a lower price per port. A Cyclone device can be used with Intel IP cores, such as the 10/100 Ethernet MAC controller core, to reduce design time. The Nios® II embedded processor can be used to perform some of the control functions within the system. The integration of various discrete devices into a single Cyclone device decreases the number of components on board and also reduces design cost and time. Cyclone devices have a highly efficient device architecture and meet the performance and price requirements of cost-sensitive communication test products. The low-cost Cyclone devices used in combination with Intel IP cores can lead to shortened development cycles for faster time to market and significant cost savings.
Intel offers a variety of IP cores that can be utilized in tester equipment. High-speed chip-to-chip interfaces such as SFI, SPI3, SPI4.x, SGMII, and XAUI, and memory interfaces such as DDR3 and RLDRAM III can be downloaded from IP MegastoreTM website.