Semiconductor automated test equipment (ATE) consists of various instruments or cards used for testing memory, digital, mixed signal, and system-on-a-chip (SoC) components, both at the wafer and packaged stages. Driven by the demand in the consumer, computing, and communication markets, these test systems continue to evolve. To keep pace with innovation in the semiconductor industry, today’s ATE products must provide more functionality at higher speeds than ever before.

Programmable logic plays an important role in the development of ATE products by providing flexibility and scalability. Functions such as timing accuracy, memory control, digital signal processing (DSP) analysis, high-speed I/O capability, and jitter compliance are all served by programmable logic. Figure 1 shows a typical instrument card in an ATE system. With the increasing complexity of ATE products, more intellectual property (IP) continues to be integrated within the programmable logic.

Intel offers a variety of IP cores that can be utilized in ATE products. Memory interfaces such as DDR3 and RLDRAM III, or high-speed bus interfaces such as PCI Express® (PCIe®), SFI, and SerialLite (a lightweight, high-bandwidth, point-to-point data protocol) can be downloaded from the Intel® IP MegaStore® website.

Figure 1. Typical ATE Test Station

Solutions

The feature-rich architecture of Intel's Stratix®Arria® and Cyclone® device families provides an excellent solution for ATE production. These device families give system designers flexibility, performance, integration, and design resources that are not available in any other device solution. These silicon products, combined with Intel’s extensive portfolio of IP cores, provide designers with industry-leading solutions for the development of next-generation ATE platforms.

Stratix series FPGAs use a high-performance architecture that accelerates block-based designs for maximum system performance. Stratix series devices include high-performance, high-precision DSP blocks, up to 52 Mb of embedded memory, up to 950K equivalent logic elements (LEs), and flexible I/O standards.

Built on the award-winning Stratix architecture, Stratix series devices include the embedded memory and LE resources needed for input and output pin processing functions, such as signal synchronization and timing analysis. The Stratix device series integrates 28.05 Gbps transceivers and up to 66 full-duplex transceiver channels supporting data rates of 14.1 Gbps, with the signal integrity required for serial protocols such as PCIe Gen3.

Arria® FPGA series include unique innovations such as an embedded dual-core ARM® CortexTM-A9 MPCoreTM processor. This hard processor system (HPS) includes a rich set of hardened peripherals, the lowest power transceivers at 6.5536 Gbps and 10.3125 Gbps, hardened memory interfaces, and a power-optimized core architecture that comprises redesigned adaptive logic modules (ALMs), variable-precision DSP blocks, distributed and new M10K embedded memory blocks, and fractional clock synthesis phase-locked loops (PLLs).

Intel offers a variety of IP cores that can be utilized in tester equipment. Chip-to-chip interfaces and memory interfaces such as DDR3 and RLDRAM III can be downloaded from Intel's IP MegaStore website.

For applications requiring a lower price per pin, the Cyclone FPGA series of high-density, low-cost devices are a precise fit. Cyclone devices can be used in conjunction with Intel IP cores, such as the Nios® II embedded processor, to implement control functions that significantly shorten design time. This embedded IP function can shorten development cycles, lower costs, and yield faster time to market. The integration of various peripherals into a single Cyclone series device reduces the number of discrete components on boards, along with related design costs and time, leading to significant cost savings. With a highly efficient device architecture, Cyclone series devices meet the performance and integration needs of ATE products.

Table 1. IP, Development Kits, and Reference Designs