Today’s wireless infrastructure is built around heterogeneous networks comprised of many different-sized radios, ranging from Macro and Metro to Pico and Femto cells, as shown in the following figure.
Each of these cells exhibits widely different requirements, including:
- RF output power level (typically 125 mW to 80 W)
- Number of antennas (typically 2 to 8)
- Number of bands (700 MHz to 3.5 GHz and beyond)
- Number of carriers (single to eight)
- Number of users
- Configuration (integrated antenna, remote radio head, traditional, active antenna arrays)
- Form factor and power consumption (-48V, PoE, AC, DC)
- Technology (GSM, CDMA, UMTS, LTE, LTE-A, 5G)
To provide solutions for their networks, operators need to draw upon a broad range of radio hardware. Equipment manufacturers desire scalable, flexible platform solutions to minimize design effort, cost, and time to market. Scalability also helps minimize test time and inventory, and maximize design reuse. Scalable platform solutions are also desirable because they allow operators to quickly adopt to changing standards and to the evolving performance requirements characteristic of modern wireless communications.
The key components of digital radio IP are Digital Up Conversion (DUC)/Digital Down Conversion (DDC), Crest Factor Reduction, and Digital PreDistortion (DPD). Altera FPGAs and SoC devices provide a flexible, cost-effective and scalable platform for implementing digital radios. New requirements and design fixes can be adopted rapidly and targeted at different radios.
Altera’s Quartus® Prime design software includes DSP Builder Advanced (DSPBA). Leveraging Matlab and Simulink, this tool allows engineers to design entire digital front ends in a system-level modeling environment and then target the Altera FPGA of their choice. Quartus Prime place and route tools are fully integrated, allowing designers to rapidly explore different implementation options in order to find the most efficient solution. Designs can be easily optimized to make the best use of the available resources and clock speeds.
Altera’s Quartus Prime design software also includes QSYS. This top-level integration tool allows the designer to build their top-level design by connecting IP blocks, including DSPBA, using Avalon streaming and memory interfaces. From this point designers can construct a complete memory-mapped register file that can be directly interfaced to an internal SoC processor sub-system or external host.
To further accelerate the design process, Altera also provides a multitude of HW Dev Kits, Reference Designs and IP blocks.