The Ethernet standard has evolved in the enterprise, service provider, and the data center segments due to the increase in packet-based protocol traffic from video and mobile applications. Altera is committed to provide Ethernet solutions for these vertical segments through its silicon innovation and intellectual property (IP) offerings to enable customers to create differentiated products and stay ahead in time to market.
Altera’s Stratix® 10 FPGA transceivers run up to 30 Gbps, enabling support for a wide range of Ethernet protocol data rates starting from 10/100 megabits per second (Mbps) and 10/100/1000 Mbps to 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE). Altera’s Stratix series FPGA transceivers with superior signal integrity (SI) and on-chip signal conditioning functions enable direct interface with SFP+, XFP, QSFP, CFP, CFP2, and CFP4 optical modules. Embedded within the transceivers are dedicated hardened physical coding sublayer (PCS) functional blocks such as encoding and decoding, block sync and word sync, and clock rate compensation to enable higher system integration for Ethernet applications.
Altera provides a wide range of configurable 10G local area network (LAN) PHY, 10G wide area network (WAN) PHY Ethernet media access control (MAC), and TCP/IP acceleration solutions used in FPGA designs.
The Ethernet MAC layer cores, that are designed to the IEEE 802.3 standard, support automated pause frame handling, IEEE 802.1q VLAN tagged frames, and jumbo frames though optional configuration register bits. Several parallel PHY interfaces, such as GMII, RGMII, RMII, TBI, and RTBI, and serial PHY interfaces, such as SGMII and SMII, are supported, allowing flexible interconnection to any optical and copper link technology. These high-level, pre-packaged, proven silicon IP cores and reference designs are compatible with various Ethernet standards including 802.3, 802.1Q, 803.3ae, and 802.3ah.
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- Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs (PDF)
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- 10-Gigabit Ethernet & HiGig-to-SPI-4.2 Bridge Reference Design
- Metro Ethernet Forum