FPGAs provide an efficient, reconfigurable platform for implementing many different types of multiport peripheral device protocol aggregation and switching solutions. Altera® devices support many different electrical interfaces of various full-duplex device protocols, with flexible parallel I/Os and dynamically reconfigurable serial transceivers. These devices also embed single- and dual-port memory structures that can be configured for various packet and cell buffering architectures. These features provide the foundation for dynamically reconfigurable, full-duplex protocol conversion solutions. In addition, Altera and our partners offer a broad range of interface protocol intellectual property (IP) solutions that can satisfy the needs of a broad spectrum of applications and leverage the integrated transceivers in our FPGA devices. You can overcome interoperability issues that come from devices with different interfaces using Altera's protocol bridging solutions, as seen in Figure 1. With the combination of device capability and IP offering, you can have the full flexibility of any device configuration as you are architecting your system, resulting in more efficient silicon reuse, faster time to market, and reduced component cost.

Figure 1. Devices with Different Interfaces Using Altera's Protocol Bridging Solutions

Figure 1 Protocol Bridges page showing 3 different scenarios that a bridge FPGA is needed to connect 2 devices with different interfaces

Optimized for high bandwidth, Stratix Series FPGAs are well-suited for protocol bridging applications. The devices come with up to 144 full-duplex serial transceiver channels at speeds up to 30 Gbps, and transceivers at speeds up to 28.05 Gbps. An enhanced adaptive logic module packs in substantially more logic and eases timing closure on register-rich and heavily pipelined designs. Embedded HardCopy® Blocks enable hardened logic-intensive functions like PCI Express® Gen3/Gen2/Gen1 and Interlaken physical coding sublayer (PCS) in a more power- and space-efficient area of the silicon. From this, you get more functionality in a smaller device, with lower power and cost.