Altera and MathWorks have collaborated to deliver a suite of design tools aimed at providing seamless integration of system models developed in MATLAB and Simulink with Altera® FPGAs and SoCs.

Engineers using MATLAB and Simulink for system modeling, algorithm development, visualization, and advanced debugging can easily target Altera FPGAs. In addition, they can be guaranteed that code generated will be optimized and ready for deployment and production.

In particular, Altera and MathWorks have partnered for the following key products:

  • HDL Coder 
    Automatic Verilog/VHDL intellectual property (IP) core generation and system integration from MATLAB and Simulink for Altera FPGAs and Altera SoCs.
  • Embedded Coder 
    Automatic C-code generation and system integration from MATLAB/Simulink geared toward Altera SoCs.
  • DSP Builder 
    Automatic hardware description language (HDL) code generation from Simulink for designers using model-based design. The DSP Builder generates target-optimized VHDL from Simulink, and its unique fused datapath flow provides highly optimized implementation of floating-point models. The HDL Coder and DSP Builder have been integrated through technical collaboration between Altera and MathWorks, enabling designers to generate HDL from Simulink models that include hierarchical subsystems built in the DSP Builder.
  • HDL Verifier 
    Includes verification of HDL against testbenches created in MATLAB and Simulink via FPGA-in-the-Loop verification with Altera FPGA and SoC boards.