GEDEK (Ethernet Data Exchange Kit)

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Qsys Interconnect: Interrupt

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

GEDEK is the easiest and best performance solution to exchange data reliably over Ethernet. It is a hardware solution, very compact, tha does not require any processor nor embedded software while offering 100% bandwidth. Available for 100M, 1G, Triple speed Eth. An 10G version is also available.

Features

  • * 100% bandwidth efficiency, no data loss.
  • * Extremely compact.
  • * Flexible license schemes
  • * Affordable

Device Utilization and Performance

Can be as low as 2k Logic Elements.

Getting Started

Start by reading the Introduction document at http://www.alse-fr.com/IPs/GEDEK_Intro.pdf

IP Quality Metrics

Basic
Year IP was first released2009
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Behavioral ETh model with file I/O, PC API (Linux & Windows), misc language examples (C, Borland, Po
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux, Windows
Implementation
User InterfaceAvalon-MM; Other: Avalon ST
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim Intel Edition, other simulators ok.
Hardware validated Y. Altera Board Name more than 10x different Intel & partners boards & Kits
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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