HyperRAM Controller

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The new HyperRAM memories, based on low-power PSRAM technology, are very welcome addition to the traditional RAM memories portfolio. They provide good bandwidth performance while using a limited amount of pins. The interface, known as « HyperBus », offers a low signal count (Address, Command and Data using only eight DQ pins), Low Power consumption, Hidden Refresh, Automotive Temperature. These memories are optimized for Mobile and Automotive applications. Typical power consumption during burst read is about 60mA. ALSE has then designed a very-low resource usage HyperBus Memory Controller, in order to provide an easy interface to the HyperRAM memories, along with high performance (up to 333 MBytes/s, which is x1.5 times faster than a 16 bits PSRAM running @ 108MHz).

Features

  • Up to 333MBytes/s, with only 12 pins used and only 60mA power consumption
  • Very low resource usage, enabling IP integration in the smallest FPGA
  • Burst Oriented access, for optimized access and bandiwdth
  • User Access to HyperRAM registers, to configure memory settings (Output drive strength, Burst wrap, etc ...)
  • Sophisticated SDC Timing Constraints, for easy Timing Convergence. Easy integration thanks to QIP file.

Device Utilization and Performance

Cyclone 10 LP : around 300 LEs, 2 M9Ks. Up to 166MHz clocking.

Getting Started

Contact ALSE to evaluate our solution on your own board, or on an Intel Dev Kit. ALSE can provide a Hardware Tester reference design, and the customer can also use an Intel FPGA IP Evaluation mode (formerly known as OpenCore Plus) version of the IP.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
QIP File, hw_tcl for Qsys / Platform Designer integration
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNo Software needed
Implementation
User InterfaceAvalon-MM; Other: AXI can be provided
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim Intel Edition
Hardware validated Y. Altera Board Name Cyclone 10 LP FPGA Evaluation Kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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