JPEG streaming Encoder

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

This JPEG-Encoder IP has been designed for easy integration into all kinds of FPGAs. It has been highly optimized for a very small footprint and an excellent Fmax, enabling the use of low cost FPGAs. This IP enables FPGA-based applications to outperform DSP-based solutions and to address the most challenging markets. The JPEG-Encoder IP can compress Still Images and Video Streams and it comes with Raster-to-Block conversion integrated. Several popular input formats are supported natively (BT656, YUV, RGB), thus simplifying the connection to various image sensors or video streaming sources (Video Codecs, Ethernet streams etc). Deliverables include a very sophisticated HDL simulation environment for seamless development, verification and integration in the final application.

Features

  • Baseline JPEG-Encoder
  • Many input formats (including YCbCr, RGB, BT656 etc), Parallel Inputs, Avalon-ST, AXI4
  • Dynamically configurable quantization tables (up to 8 tables) for multiple levels of compression.
  • Dynamic choice of compression level
  • Streaming encoder : extra low latency !

Device Utilization and Performance

Encoder alone is ~3700 LEs or 1700 ALMs, 7 to 15 Memory blocks, 4 multipliers. Fmax > 170MHz on low-cost Cyclone IV-CV.

Getting Started

Demos are available on many existing boards, including AVDB / Clovis ! Demo available on low-cost Max10 DECA kit. Contact A.L.S.E

IP Quality Metrics

Basic
Year IP was first released2012
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
QIP File for Easy Integration
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportno driver required
Implementation
User InterfaceAXI; Avalon-MM; Other: Avalon ST-video
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name AVDB / Clovis and many others
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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