PSRAM Memory Controller

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

Power consumption is more and more critical in many applications, such as battery-powered equipments, very low power applications and other fields like automotive, military, etc … Thus, choosing and using a very low power external memory such as a PSRAM (Pseudo-Static RAM) memory can be a very interesting solution (less than 40 mA during burst read operations @ 104 MHz) ALSE has developed a very compact and efficient controller that can be easily integrated in any FPGA project.

Features

  • High-Performance Controller supporting Burst Mode for Read/Write transfers
  • Support of different PSRAM memory standards (e.g : Micron CellularRam 1.0/1.5/2.0)
  • Support of PSRAM memory with Multiplexed address/data bus
  • Easy integration using Altera Qsys, or manually.
  • Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs, etc…

Device Utilization and Performance

Typically less than 300 LEs, and 2 Memory Blocks. Memory Operating Frequency > 100 MHz, depending on FPGA / Memory speed grades, and customer PCB characteristics.

Getting Started

Contact A.L.S.E for a demonstration on your board.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
QIP File for Easy Integration
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportno driver required
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Customer board
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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