Quad-SPI Serial Flash Memory Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

Quad-SPI Flash memories have many advantages : high speed, low pin count, small packages, and low cost ! ALSE Quad-SPI Flash Controller IP has been designed for ultimate performance, small footprint and easy integration in all kinds of FPGAs, low-cost to high-end. Dramatically reduce the boot time, store streaming video, or even run processor code directly from the Flash, etc. The unique CFI Emulation (optional) feature further facilitates the adoption of Serial Flash memories. Supports all types of Quad SPI Flash Memories. Deliveries include a HDL simulation environment for seamless integration in any project. Our Quad-SPI controller has been used successfully by many customers in different contexts, always delivering outstanding performance.

Features

    Device Utilization and Performance

    Including Flash Programming : ~1,100 LEs, or ~500 ALMs, 1 Memory block Fmax 175MHz on Cyclone III and 230 MHz on Stratix V

    Getting Started

    For additional information, contact ALSE : http://www.FPGA.fr !

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportCFI emulation
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Most Altera FPGA kits using a Quad-SPI, AVDB, BeMicro-Max10 etc
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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