Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc … Synchronous SRAM memories are very good candidates for such latency-sensitive applications, thanks to their (very) low latency (typically one clock cycle), high performance. Interfacing such memories to an FPGA is easy using to the optimized ALSE controller. Thanks to its very small FPGA footprint and low resource usage, this controller fits in the smallest FPGAs, which makes it also perfect for the Automotive and Consumer Markets.
- High-Performance Controller supporting Burst Mode for Read/Write transfers
- 100% bandwidth use with Specific version of the controller for No Bus Latency memories (Zero Wait States memories)
- Very low FPGA resource usage : less than 200 Logic Cells, and two memory blocks
- Easy integration using Altera Qsys, or manually.
- Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs, etc…
IP Quality Metrics
|Year IP was first released||2011|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||QIP File for Easy Integration|
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||N|
|Driver OS support||no driver required|
|IP-XACT Metadata included||N|
|Hardware validated||Y. Altera Board Name Customer board|
|Industry standard compliance testing performed||N|
|If No, is it planned?||N|
|IP has undergone interoperability testing||Y|
|Interoperability reports available||N|
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