SSRAM Memory Controller

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc … Synchronous SRAM memories are very good candidates for such latency-sensitive applications, thanks to their (very) low latency (typically one clock cycle), high performance. Interfacing such memories to an FPGA is easy using to the optimized ALSE controller. Thanks to its very small FPGA footprint and low resource usage, this controller fits in the smallest FPGAs, which makes it also perfect for the Automotive and Consumer Markets.

Features

  • High-Performance Controller supporting Burst Mode for Read/Write transfers
  • 100% bandwidth use with Specific version of the controller for No Bus Latency memories (Zero Wait States memories)
  • Very low FPGA resource usage : less than 200 Logic Cells, and two memory blocks
  • Easy integration using Altera Qsys, or manually.
  • Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs, etc…

Device Utilization and Performance

Typically less than 200 LEs, and 2 Memory Blocks. Memory Operating Frequency up to 200 MHz, depending on FPGA / Memory speed grades, and customer PCB characteristics.

Getting Started

Contact A.L.S.E for a demonstration on your board.

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
QIP File for Easy Integration
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportno driver required
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Customer board
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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