H264 Encoder Micro Footprint

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore

Technology: DSP: Transforms

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

H.264 ENCODER FPGA Core - High Speed Micro Footprint Our FPGA core is highly optimized and 80% SMALLER AND FASTER THAN THE COMPETITION WITH ⟨ 1ms LATENCY @ 1080p30! It is capable of being synthesized in many FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 1.5 clocks/pixel. Multiple cores can be used for processing larger size or higher frame rate images. Uses FPGA specific DDR 3 controller and microprocessor soft core. In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs.

Features

  • 1.5 clocks/pixel processing rate
  • Supports resolutions up to 4096 x 4096 (can be expanded with additional cores)
  • Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
  • Generates I and P frames
  • Variable Bit Rate (VBR) and Constant Bit Rate (CBR)

Device Utilization and Performance

ALMs: 28,000 Combinational ALUTs: 34,000 Dedicated Logic Registers: 50,000 Block Memory Bits: 285,000 M10Ks: 390 DSP Blocks: 30 Frequency : 98MHz

Getting Started

Please contact us at sales@A2eTechnologies.com for pricing information and any other questions

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported14.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference design based upon Cyclone V SoC
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux 3.9
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name Cyclone V SoC Terasic P0160
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.