10GE MAC

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria 10 SoC

Stratix Series: Stratix V

Overview

Algo-Logic Systems' ultra low latency (ULL) 10GE MAC minimizes roundtrip latency by several hundred nanoseconds as compared to vendor supplied IP cores. It is compatible with Altera's PHY to make a complete solution: PHY+MAC. The design implements 10GBASE-R MAC and PCS (Physical Coding Sub-layer) functionality in an FPGA by using logic optimized for latency. The ULL PHY+MAC supports SERDES rates of 10.3125 Gbps while bypassing all PCS and excessive buffering features. The MAC interfaces to user logic via the 64-bit Avalon-ST bus or AXI4-Stream standards. The Ethernet Frame Check Sequence (FCS) within the transfer is automatically added in the transmit direction; the FCS is checked, indicated, and removed in the receive direction. The only padding done is on the transmit side (Tx) if the transmitter MAC sees fewer than 60 bytes. On the receive side (Rx), the MAC passes the packet that it receives without change.

Features

    Device Utilization and Performance

    Device utilization on Stratix V A7 is: 1. Wire to wire latency: 89.6nS 2. Registers: 1915 3. Logic utilization: 1689 ALMs 4. Block memory bits: 0

    Getting Started

    Please visit http://algo-logic.com/phymac for more information or contact solutions@algo-logic.com

    IP Quality Metrics

    Basic
    Year IP was first released2014
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNo CPU needed
    Implementation
    User InterfaceOther: Avalon ST
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim, VCS, NCSIM
    Hardware validated Y. Altera Board Name Terasic DE5-Net, Nallatech P385, Nallatech P385A, Bittware S5PH-Q
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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