PCIe Solutions

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10

Stratix Series: Stratix V

Overview

Algo-Logic's low latency PCI express (PCIe) solutions rapidly transfer data between FPGA logic, processors, and memory. For example, in many High Frequency Trading (HFT) systems and datacenter applications, rapid data transfers are needed between FPGA logic and the Order Management System (OMS) software. For these frequent and short transactions, Algo-Logic's PCIe solutions are optimal for minimizing latency. Algo-Logic's PCIe solutions are plug-and-play; the hardware interfaces and software APIs are easy to use for software developers building low latency network streaming applications. The Register Interface supports a low latency host to FPGA communication through memory-mapped I/O (MMIO) with write combining. The Direct Memory Access (DMA) Engine is specifically designed for kernel-bypass Linux applications that require high throughput and low latency.

Features

    Device Utilization and Performance

    For PCIe solutions, the device utilization on Stratix V A7 device is: 1. 15956 ALMs 2. 19718 registers 3. 1063424 block memory bits 4. Median Latency Host to FPGA RT: 1 microseconds for 300 Byte datagram* 5. P99 Latency Host to FPGA RT: 1.26 microsecond for 300 Byte datagram* * Test configuration: 256 bit wide bus at 156.25Mhz clock domain on Intel i7 at 3.5Ghz.

    Getting Started

    Please visit http://algo-logic.com/PCIe for more information or contact solutions@algo-logic.com

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportLinux
    Implementation
    User InterfaceOther: Avalon ST
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Nallatech P385, Nallatech P385A
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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