Alizem 3-phase PWM IP Core for Intel MAX 10 FPGA

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

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Supported Device Family: 

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Overview

Alizem 3-phase PWM IP Core is meant to be easily, quickly and safely integrated into an Intel® MAX® 10 FPGA for use in many inverter-based (DC-AC) power electronics applications: pump and fan electric motor control, solar power conversion and power supplies. It is the first building block of any control system meant to drive a 3-phase 2-level inverter (6 switches) or intelligent power module (IPM).

Features

    Device Utilization and Performance

    Each instantiation is taking under than 100LEs on MAX 10 FPGA. Complete reference design (including NIOS II processor) is under 2300 LEs, i.e. fits on the smallest MAX10 FPGAs.

    Getting Started

    1- Download datasheet for FREE on Alizem website: www.alizem.com/PWM 2- Choose version (demo, low-volume, IoT or source code) and download the software directly from the website. 3- At the same time, you can download Alizem ebooks on custom electric motor drive design and MAX 10-based embedded system design.

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported17.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportAltera HAL
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim
    Hardware validated Y. Altera Board Name Intel MAX 10 FPGA Development kit
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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