16-port G.Fast Switch Codechip - G.999.1 Connectivity

Block Diagram

Solution Type: IP Core

End Market: Industrial, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

Arrive G.Fast Switch Codechip provides two uplink ports up to 10 Gb/s and four G.999.1 ports at rate of up to 2.5 Gb/s. The FPGA-based SoC solution and external front-end devices can help to make quick-to-market distribution point equipment, specifically for Fiber-to-the-Distribution-Point (FTTdp) or to bring gigabit speeds to multiple dwelling unit (MDU) applications in access networks. Arrive's CodeChips are provided in fully complete bitstream or encrypted netlist format along with firmware device driver/software API packages, BSP, schematic and layout reference design files, design reviews, board testing and support from initial project definition to mass production. The CodeChip bitstreams and encrypted netlists are targeted to specific FPGA devices that are selected based on the mix of features requested and customer preference. CodeChips are provided with CodeChip API as a single API software driver for all CodeChip variants. CodeChip API supports protocol stack handling.

Features

    Device Utilization and Performance

    Contact Arrive for more information

    Getting Started

    Contact Arrive for more information

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportOS independent
    Implementation
    User InterfaceOther: Contact Arrive
    IP-XACT Metadata includedN
    Verification
    Simulators supportedContact Arrive for more information
    Hardware validated Y. Altera Board Name Contact Arrive for more information
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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