STM16 CES/CEP CodeChip

Block Diagram

Solution Type: IP Core

End Market: Industrial, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Stratix Series: Stratix IV, Stratix V

Overview

Arrive's Pseudowire CodeChip product line offers a family of complete pseudowire and mobile backhaul CodeChip devices. Arrive provides total solutions in groupings of 1 to 16 DS1/E1/J1 or 1 to 32 DS1/E1/J1 lines; aggregation nodes with up to 84/63 DS1/E1 lines; high-density nodes with 336/252 DS1/E1 lines; or very dense nodes with 1344/1008 DS1/E1/J1 lines. The aggregation and higher density nodes use SONET/SDH interfaces for service side connection. Arrive's CodeChips are provided in fully complete Bitstream format or encrypted netlist format along with firmware device driver/software API packages, BSP, schematic and layout reference design files, design reviews, board testing and support from initial project definition to mass production. The CodeChip bitstreams and encrypted netlists are targeted to specific Altera devices that are pre-selected based on the mix of features requested.

Features

    Device Utilization and Performance

    Contact Arrive for more information

    Getting Started

    Contact Arrive for more information

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportOS independent
    Implementation
    User InterfaceOther: Local CPU buses
    IP-XACT Metadata includedN
    Verification
    Simulators supportedContact Arrive for more information
    Hardware validated Y. Altera Board Name Arria V
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?Contact Arrive
    If yes, on which Altera device(s)?Arria V
    If Yes, date performed
    04/02/2012
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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