EXP-E5200 - High Performance PKA/RSA/ECC Security Processor

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V


From the leaders in Public Key Acceleration comes the fourth generation of Athena's TeraFire PK line, the E5200 Public Key Microprocessor. The E5200 includes hardware accelerated P-Curve EC, delivering both the fastest RSA and the fastest EC operations of any core on the market. The E5200 uses Athena's proprietary PK instruction set architecture, enabling any PK operation, including RSA, DSA, DH, ECDH, ECDSA, and the myriad other elliptic curve cryptography algorithms. This powerful, flexible instruction set can easily accommodate new standards with on-the-fly programmability, ensuring that your application will always be able to handle new requirements and protocols.


    Device Utilization and Performance

    Less than 11K ALUTs

    Getting Started

    From the market leader in high performance public key cryptography cores comes the 5200 series, a fast and efficient public key cryptography solution with multiple size and performance options that can be matched to the requirements of your application. Athena’s patented arithmetic technology delivers the performance your solution needs – low latency and high throughput – in an area-efficient IP Core portable to any Altera device.

    IP Quality Metrics

    Year IP was first released2008
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    by request
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportLinux, OpenSSL
    User InterfaceAXI; Other: AHB
    IP-XACT Metadata includedN
    Simulators supportedall
    Hardware validated Y. Altera Board Name Cyclone V, Stratix V, Arria 10
    Industry standard compliance testing performed
    If yes, which test(s)?NIST CAVP
    If yes, on which Altera device(s)?Cyclone V
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  N

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