High Performance AES - Advanced Encryption Standard

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V


Athena delivers the Advanced Encryption Standard (AES) ciphers as semiconductor intellectual property (IP) cores. Athena’s AES cores complement the market-leading TeraFire® cryptography microprocessors and standalone TeraFire cryptography accelerators. Whether your application demands high AES performance or the power savings of a dedicated core, Athena’s AES cores deliver both performance and power savings.


    Device Utilization and Performance

    ~3 Gbps, ~650 ALUTs

    Getting Started

    Dedicated AES core solutions are constructed using a modular architecture, comprising cipher cores, key schedule generators, and modes modules, allowing Athena to configure an AES solution optimized for the functional, performance, area, and power requirements of your application. Athena supports all AES modes, including ECB, CBC, CFB, OFB, CTR, CMAC, CCM, GCM, and GHASH, and even XTS mode (SP800-38E). Any modes and/or key sizes not required can be omitted to reduce area.

    IP Quality Metrics

    Year IP was first released2008
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    By Request
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportLinix, OpenSSL
    User InterfaceAXI; Other: AHB
    IP-XACT Metadata includedN
    Simulators supportedall
    Hardware validated Y. Altera Board Name Cyclone V, Stratix V
    Industry standard compliance testing performed
    If No, is it planned?Y
    IP has undergone interoperability testing
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.