JPEG Baseline Encoder (BA116)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The JPEG intellectual property (IP) core is intended for high-speed encoding of grayscale, color, or multi-scan images using ISO/IEC 10918-1 baseline coding standard. The encoder supports all features of the baseline standard, including restart markers, DNL, user-definable comments and application markers. The BA116 is able to encode abbreviated-format or full-format images. If preferred, pre-defined default entropy and quantization tables are available. Its autonomous behavior, simple FIFO-like interfaces, and 100% synchronous structure, allow easy integration of the IP into complex systems with little effort. The ease of integration of this powerful IP core is reinforced by the stand-alone ability of the encoder that can be used in systems with very little CPU intervention.

Features

    Device Utilization and Performance

    Please contact Barco Silex to receive accurate estimation based on your application requirements and FPGA device.

    Getting Started

    Please contact Barco Silex to evaluate the JPEG encoder IP core and receive additional information.

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Bit-accurate software model of the JPEG encoder
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS support-
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedMentor Graphics, Synopsys and Cadence
    Hardware validated N. Altera Board Name DK-DEV-4SGX230N
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.