Public Key IP Core for RSA, ECC, ECDSA and ECDH...

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The Public Key Cryptography IP core is a versatile IP core for all asymmetric cryptographic operations. The Public Key IP core is the perfect companion to your processor or microcontroller. It executes operations completely stand-alone. The host controller doesn’t need to interact with the Public Key IP core except for configuring the operation and reading out the result. This is also true for higher level operations such as ECDSA and DH. The core processing unit is scalable in performance and resource allowing both very high performance and very small configurations. The granularity of these configurations guarantees the best trade-off between technology, performance and area.

Features

    Device Utilization and Performance

    The Public Key IP core is scalable. Please contact Barco Silex to receive accurate estimation based on your application requirements and FPGA device.

    Getting Started

    Please contact Barco Silex to evaluate the Public Key IP core and receive additional information.

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportLinux, bare-metal
    Implementation
    User InterfaceAXI; Other: BT656-like
    IP-XACT Metadata includedN
    Verification
    Simulators supportedMentor Graphics, Synopsys and Cadence
    Hardware validated Y. Altera Board Name Cyclone V Development Kit, Socrates
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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