True Random Number Generator (TRNG)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Basic Functions: Miscellaneous

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The Random Number Generator (BA431) is an essential IP core for all FPGA and SoC designs that target cryptographically secured applications. The BA431 includes a True Random Generator (TRNG) as the source of entropy. The optional Deterministic Random Bit Generator (DRBG) can be provided with the core. The entropy source and theDRBG are designed for compliance with the NIST 800-90A and NIST 800-90B draft. It is easily portable to any Altera device (FPGA and SoC). The IP core successfully passes NIST 800-22 and AIS31 test suites and has already passed FIPS 140-2 certification.

Features

    Device Utilization and Performance

    The TRNG is a small IP core that can fit in any device. Please contact Barco Silex to receive accurate estimation based on your application requirements and FPGA device.

    Getting Started

    Please contact Barco Silex to evaluate the TRNG IP core and receive additional information.

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportLinux, bare-metal
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedMentor Graphics, Synopsys and Cadence
    Hardware validated Y. Altera Board Name Cyclone V Development Kit, Socrates
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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