Bigstream Hyper-acceleration Layer

System Diagram

Arria Series: Arria 10

Altera: Intellectual Property: Compiler Tool; Segment: Artificial Intelligence, Cybersecurity, Data Analytics, Financial, Genomics, Networking, Video

Overview

Bigstream makes Big Data, Machine Learning and AI workloads faster through a technique called Hyper-acceleration. Bigstream developed Hyper-acceleration to deliver orders of magnitude performance gains for Apache Spark using hardware and software accelerators. Hyper-acceleration of big data and machine learning workloads is achieved using advanced compiler technology and transparent support for FPGAs. Unlike other approaches, Bigstream requires no application code changes or special APIs. Hyper-acceleration is a technology that enables big data and machine learning applications automatically utilize the power of unconventional hardware (e.g. GPUs, FPGAs) as well as software optimizations with many-core CPUs. The Bigstream Hyper-acceleration Layer (HaL) functions as a runtime system that sits between a software platform (such as Apache Spark, or TensorFlow) and the underlying hardware to slice and distribute the computation between traditional CPU cores and different accelerator resources like FPGAs and GPUs. There are a lot of approaches to accelerating some stages of a big data workload, but our approach is transparent to end users – in this case, data scientists, BI teams and application developers.

Features

  • In-line, zero copy processing: hyper-efficient in-line processing of data in motion, avoiding unnecessary data copying or movement
  • FPGA/GPU acceleration: automatic hyper-acceleration of compute-intensive tasks on FPGAs, CPUs, and GPUs without requiring special skills
  • Support for well established big data platforms: expanding support for popular big data platforms like Spark, Kafka, and TensorFlow
  • Zero code changes: seamless, automatic process requiring no special training, APIs or code changes
  • Native execution: accelerated execution of big data platforms without the overhead of JVM/garbage collection

Validated for use with

Basic
Quartus Prime Pro Version 17.0
Acceleration Stack version 1.0 Alpha
Xeon + FPGA Platforms supported Intel® Programmable Accelerator Card with Intel® Arria® 10 GX FPGA
Device Family Arria 10
Cloud Deployments undefined

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