Bitec HDMI 2.0a IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: HDMI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V


The Bitec HDMI 2.0 IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using minimal device i/o pin resources. The core can operate in 1-, 2- and 4.symbols per clock allowing for high pixel rates on low end FPGA devices


    Device Utilization and Performance


    Getting Started


    IP Quality Metrics

    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNOT APPLICABLE
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Simulators supportedCadence, Synopsis and Mentor
    Hardware validated Y. Altera Board Name Arria 5
    Industry standard compliance testing performed
    If yes, which test(s)?HDMI CTS
    If yes, on which Altera device(s)?Arria
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  Y

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