Bitec HDMI 2.0a IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: HDMI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Bitec HDMI 2.0 IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using minimal device i/o pin resources. The core can operate in 1-, 2- and 4.symbols per clock allowing for high pixel rates on low end FPGA devices

Features

  • HDMI 2.0a and 1.4a Compatible
  • 1-,2- or 4- symbol/pixel per clock input/output
  • 2-, 8- and 32-channel Audio support
  • Optional CEC 1.4 and 2.0 support
  • Optional HDCP 1.4/2.2 support

Device Utilization and Performance

TBD

Getting Started

TBD

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNOT APPLICABLE
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedCadence, Synopsis and Mentor
Hardware validated Y. Altera Board Name Arria 5
Industry standard compliance testing performed
Y
If yes, which test(s)?HDMI CTS
If yes, on which Altera device(s)?Arria
If Yes, date performed
08/01/2015
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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