V-by-One HS

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: Basic Functions: I O

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

V-by-One HS was developed by THine Electronics, Inc.(http://www.thine.co.jp) to support the higher frame rates and the higher resolutions required by advancing FPD technology, while reducing costs and time-to-market.

Features

    Device Utilization and Performance

    TBD

    Getting Started

    TBD

    IP Quality Metrics

    Basic
    Year IP was first released2014
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNOT APPLICABLE
    Implementation
    User InterfaceOther: VIDEO
    IP-XACT Metadata includedN
    Verification
    Simulators supportedCadence, Synopsis and Mentor
    Hardware validated N. Altera Board Name Arria 10, Arria 5 and Stratix 5
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?PHY
    If yes, on which Altera device(s)?Arria
    If Yes, date performed
    08/01/2014
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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