BittWare's S5-PCIe-HQ (S5PH-Q) is a half-length PCIe x8 card based on the high-bandwidth, power-efficient Altera Stratix V GX or GS FPGA. Designed for high-end applications, the Stratix V provides a high level of system integration and flexibility for I/O, routing, and processing. Over 16 GBytes of on-board memory includes DDR3 and QDRII/II+. Two front-panel QSFP+ cages allow two 40GigE interfaces (or eight 10GigE) direct to the FPGA for reduced latency, making the board ideal for high frequency trading and networking applications. The S5PH-Q also features a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management. All of these features combine to make the S5PH-Q a versatile and efficient solution for creating and deploying high-performance FPGA computing systems.
- Dual QSFP+ cages for 40GigE or 10GigE direct to the FPGA for lowest possible latency
- PCIe x8 interface supporting Gen1, Gen2, or Gen3
- Two SATA connectors; Timestamping support; Utility I/O includes: USB 2.0, RS-232, and JTAG
- High density Altera Stratix V GX/GS FPGA
- Memory options: Up to 16 GBytes DDR3 SDRAM Up to 72 MBytes QDRII/II+
- FPGA Development Kit
- Board Management Controller for Intelligent Platform Management
- Altera Quartus II software
- BittWorks II Toolkit : host, command, and debug tools for BittWare hardware; source code porting kit also available
Board Quality Metrics
|Latest version of Quartus supported||15.1|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)||N/A|
|Return Material Authorization (RMA) Policy||Contact BittWare.|
|CE Compliant||N. This is a system spec.|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
BittWare offers complete software support for the S5PH-Q with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare's boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware.
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