GZIP-RD-A10: PCIe GZIP Compression Acceleration Function

System Diagram

Arria Series: Arria 10

Altera: Intellectual Property: Accelerator Function; Segment: Data Analytics, Financial, Genomics, Networking


The GZIP-RD-A10 is a data compression acceleration function. It uses the ZipAccel-C GZIP/ZLIB/Deflate Compression IP Core and has been designed with QuickPlay® in partnership with Accelize®. The accelerator function is highly efficient and can compress data at rates exceeding 40 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth. The GZIP-RD-A10 is available as a ‘drop-in’ accelerator function for the Intel® Programmable Acceleration Card (Intel PAC) as well as other PCIe boards hosting an Arria 10 FPGA. It is delivered with a sample GUI-driven application, and is compatible with Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration in Xeon-based systems. The GZIP-RD-A10 accelerator function can be made available for Cloud FPGA instances using Accelize’s QuickStore.


  • 40 Gbps (or higher upon request) uncompressed data rate
  • High compression efficiency (comparable to software gzip-6)
  • Fully Compliant to the GZIP (RFC-1952) and ZLIB standard (RFC-1950)
  • Drop-in for Intel Programmable Card, compatible with Intel Acceleration Stack for Intel Xeon CPU with FPGAs

Validated for use with

Quartus Prime Pro Version 17.0
Acceleration Stack version 1.0 Alpha
Xeon + FPGA Platforms supported Intel® Programmable Accelerator Card with Intel® Arria® 10 GX FPGA, Bitware A10PL4, and Reflex CES XpressGXA10-LP1150B
Device Family Arria 10
Cloud Deployments OVH, and other

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