1553-BC/RT/MT: MIL-STD-1553 Bus Controller, Remote Terminal, and Monitor Terminal Core

Block Diagram

Solution Type: IP Core

End Market: Military

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

The 1553-BC/RT/MT IP core implements a serial link controller enabling the development of Bus Controllers (BC), Remote Terminals (RT), and Monitor Terminals (MT) compliant with the Department of Defense MIL-STD-1553B standard. Field-proven in many civilian and military avionics systems and optionally accompanied by a DO-254 certification package, the core is highly reliable and ready for aviation applications. The core can operate as a Bus Controller, Remote Terminal, and Monitor Terminal at the same time. The BC and RT modules can also be disabled at run time, or at synthesis time to reduce silicon requirements. The 1553-BC/RT/MT is designed to enable flexible message scheduling, monitoring, and filtering for all types of traffic in different bus architectures and with minimum overhead for the host processor. Messages are conveyed to/from the host via shared memory space organized in 16-bit words, and configure the core via its 16-bit wide register interface.

Features

    Device Utilization and Performance

    The 1553-BC/RT/MT core can be mapped to any Intel FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The core occupies approximately 6500 ALMs under its BC-only configuration, and 3000 ALMs under its RT-only configuration. Please contact CAST to discuss resource utilization and performance for your application and target device.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2008
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceOther: Generic MCU I/F
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated Y. Altera Board Name Cyclone V (designed by customer)
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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