The AES encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES32) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES128) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (ECB, CBC, OFB, CFB, CTR, CCM, GCM and LRW). The core works with a pre-expanded key, or with optional key expansion logic.
The core can be mapped to any Altera Family and optimized to suit the particular project's requirements. The AES core synthesizes to 588 ALMs for the standard version and to 2,124 ALMs for the fast version. On Arria10 device, the core can run at least 100MHz providing a throughput of 290Mbps for the standard version, or 1.16Gbps for the fast version.
IP Quality Metrics
|Year IP was first released||2002|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Bit Accurate Model|
|Parameterization GUI allowing end user to configure IP||N|
|IP core is enabled for OpenCore Plus Support||Y|
|Source language||Verilog; VHDL|
|Testbench language||Verilog; VHDL|
|Software drivers provided||N|
|Driver OS support||Not required|
|User Interface||Other: generic uP|
|IP-XACT Metadata included||N|
|Simulators supported||ModelSim, Questa, NC-SIM|
|Hardware validated||N. Altera Board Name Altera Cyclone V SOC Board|
|Industry standard compliance testing performed||N|
|If No, is it planned?||N|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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