CAMFE: Camera Front-End Processor Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: DSP: Filters

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The CAMFE Core implements a flexible, resource-efficient camera front-end processor that receives raw pixel data from a CMOS or CCD sensor and outputs a video stream ready for display, further processing, or compression. The core first converts the Bayer pattern to an RGB image using an efficient de-mosaicing interpolation filter. The interpolated RGB samples are input to the White Balancing stage, which adjusts color intensities so they are appropriate for reproduction in a display. Under its full configuration, the core subsequently proceeds with further steps essential for optimizing the visual quality of the image, running RGB to YUV color space conversion, then performing Contrast Stretching, Gamma Correction, and finally applying a Sharpening Filter. The CAMFE core does not require a frame buffer and has a small silicon footprint (~590 ALMs). Furthermore, it can process over 150 Mpixels/s even in low-end FPGAs.

Features

    Device Utilization and Performance

    CAM-FE reference designs have been evaluated in a variety of technologies. The core synthesizes to about 590 ALMs. It also requires 3 lines of buffering, that are implemented with FPGA memory resources. It is able to run over

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2014
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Software Bit-Accurate Model
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportNot required
    Implementation
    User InterfaceOther: BT656-like
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated Y. Altera Board Name DK-DEV-4SGX230N
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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