CAN-CTRL: CAN 2.0 & CAN FD Bus Controller Core

Block Diagram

Overview

The CAN-CTRL is a CAN bus controller that performs serial communication according to CAN 2.0, and CAN FD specifications. The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of buffers and acceptance filters. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The number of receive buffers and the number of STB buffers are synthesis-time configurable. An optional wrapper instantiating multiple CAN controller cores eases integration in cases where multiple bus-nodes need to be controlled by the same host processor. The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, maintenance, and optimization features. The core was proven with different transceivers and tested in CAN-FD plug-fests

Features

    Device Utilization and Performance

    The silicon resources requirements depend on the core configuration. When configured to use 3 transmit, 3 receive buffers, 3 acceptance filters, and not to support CAN-FD and TTCAN the core occupies 800 ALMs and 1,344 Memory bits. When CAN-FD is added to the above configuration, the core size grows to 1,000 ALMs and 8,960 Memory bits.

    Getting Started

    Contact CAST at info@cast-inc.com to evaluate the core

    IP Quality Metrics

    Basic
    Year IP was first released2002
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportBare-Metal Drivers
    Implementation
    User InterfaceOther: AHB-Lite, APB, Generic uP
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, Questa, NC-SIM
    Hardware validated Y. Altera Board Name DE0 Nano, CycloneV-SoC Dev. Kit
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?CAN-FD PlugFest
    If yes, on which Altera device(s)?Cyclone V
    If Yes, date performed
    04/14/2016
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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