H16550S: Synchronous 16550 UART with FIFO Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16550S can be run in either 16450- compatible character mode or in 16550- compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. The H16550S core can be utilized for many communication applications including: Serial or modem computer interface, or serial interface within modems and other devices


  • Independently controlled transmit, receive, line status and data set interrupts
  • In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
  • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
  • Capable of running all existing 16450 and 16550a software
  • Programmable baud generator

Device Utilization and Performance

The core synthesizes to about 500 LEs.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Year IP was first released2008
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportN/A
User InterfaceOther: APB, Generic uP
IP-XACT Metadata includedN
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated Y. Altera Board Name Cyclone IV, Cylcone V, Stratix IV
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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