H264-D-BP: Low-Latency AVC/H.264 Baseline Profile Decoder Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V

Cyclone Series: Cyclone V

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The H264-D-BP IP core is a video decoder complying to the Constrained Baseline Profile of the AVC/H.264 standard. It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution. The decoder adds just one macroblock line of latency, which means a negligible real-world latency under one msec for most widely used video formats, including HD/720p and Full-HD/1080p video. The H264-D-BP is designed for trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds with no assistance or input from the host processor. The decoder’s memory interface is extremely flexible: it operates on a separate clock domain, is independent from the external memory type, and is tolerant to large latencies. The decoder reports decompressed video parameters, detects and reports bit stream errors to the system, and simplifies video cropping at its output.

Features

  • ISO/IEC 14496-10/ITU-T H.264, Constraint Baseline Profile Decoder, up to level 4.1
  • Video Formats: Progressive, 4:2:0 YCbCr with 8 bits per color sample and up to 2048x2048 pixels
  • Low Latency: No decoded frame buffering - Less than 1 msec for almost all widely used video formats
  • Ease of Integration: Zero CPU overhead, stand-alone operation – AXI Interfaces
  • Silicon proven & Verified with Fraunhofer H.264 Compliance Test Streams suite

Device Utilization and Performance

The H264-D-BP core can be mapped to any Altera Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. It occupies approximately 32,000 ALMs, 19 DSPs and 532Kbits of memory, and can process 1080p30 in most Altera devices.. Please contact CAST to discuss resource utilization and performance for your application and target device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated Y. Altera Board Name DK-DEV-4SGX230N & DK-START-5AGXB3N
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.