H264-E-BPS: Low-Power AVC/H.264 Baseline Profile Encoder

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V


This is a video encoder supporting the Constrained Baseline Profile of the H.264 standard It Implements an energy-efficient hardware architecture that is optimized for ultra-low-latency video streaming at low bit rates. The H264-E-BPS requires less than half the silicon area of most competing encoder cores under 9k ALMs allowing for cost-effective FPGA implementations. Its small silicon footprint, low memory bandwidth, and zero software overhead enable H.264 coding at an extremely low energy cost. The core is able to process Full-HD video on most Altera FPGAs. Despite being small, the core produces high quality video, even at low bit-rates, and features extremely low latency. It uses a constant Qp to output VBR streams, or automatically regulates Qp to output CBR streams. In CBR mode it responds rapidly to video content changes. This can be combined with Intra-Refresh coding to effectively eliminate bit-rate peaks, while preserving the periodic intra-coded references.


    Device Utilization and Performance

    The core can be mapped to any Altera Family (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. Under its default configuration (H264-E-BPS) the core synthesizes to 8.6k ALMs, 114k Memory bits, and 9 DSP blocks. It can process 1080p30 on most FPGA devices, and upto 720p25 on Max10. The Intra-only version (H264-E-BIS) synthesizes to 5K ALMs, 58k Memory bits, and 4 DSP blocks. Higher throughputs are feasible by the H264-E-BPF core, also available from CAST.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Software Bit-Accurate Model
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportN/A
    User InterfaceAXI; Other: Simple native interface
    IP-XACT Metadata includedN
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated Y. Altera Board Name DK-DEV-4SGX230N & DK-START-5AGXB3N
    Industry standard compliance testing performed
    If No, is it planned?N
    IP has undergone interoperability testing
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.