H265-MP-D: HEVC/H.265 Main Profile Video Decoder

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Medical, Military

Evaluation Method: OpenCore

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The H265-MP-D IP core implements an HEVC/H.265 video decoder. The core complies with the Monochrome, Main, Main 10, and optionally the Monochrome 12, Main 4:2:2-10, and Main 4:2:2 12 profiles of the standard. The core is designed for trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds without any assistance from the host processor. The core uses standard AMBA interfaces: AXI-Stream for input and decoded pixel data, AXI-lite for registers access, and AXI4 for the memory controller interface The H265-MP-D is a custom hardware accelerator and uses local memories that minimize external memory bandwidth, so its power consumption and clock frequency requirements are much lower than any software, or hybrid software/hardware decoder implementation.

Features

  • HEVC Profiles: Monochrome, Main, Main-10 and optionally the Monochrome 12, Main 4:2:2 10, and Main 4:2:2 12 profiles of ITU-T H.265 | ISO/IEC 23008-2
  • Video Formats: 4:0:0 (Monochrome), 4:2:0, and optionally 4:2:2 - 8, 10, and optionally 12 bits per color
  • Performance: 1080p60 and 4k/UHD@30 depending on target FPGA

Device Utilization and Performance

A minimal configuration of the core (4:2:0 (No 4:2:2), 8bit, No long term prediction, no PCM, No Tiles support, No WPP) synthesizes to about 140k ALMs, 730 DSPs, and 2.8M memory bits . A Full configuration of the core (i.e. All coding tools, all supported video formats and profiles) synthesizes to about 150K ALMs, 730 DSPs, and 9.2M memory bits. Depending on device family and speed grade the core can support rates of 720p30/60, 1080p3-/60, and 4kUHD@30.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated Y. Altera Board Name Stratix V
Industry standard compliance testing performed
Y
If yes, which test(s)?Fraunhofer's ref. streams
If yes, on which Altera device(s)?Stratix V
If Yes, date performed
02/02/2015
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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