I2C-SMBUS Controller Megafunction

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Industrial, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V


The I2C-SMBUS megafunction implements a serial interface controller for the InterIntegrated Circuit (I2C) bus and the System Management Bus (SMBUS). The megafunction can be programmed to operate either as a bus master or slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBUS provisioned clock synchronization mechanism allows fast-master / slow-slave communication. Furthermore, the megafunction detects timeout and errors to prevent from bus deadlocks, and can filter-out glitches on the serial line. The control, status and data registers of the I2C-SMBUS megafunction are accessible via an AMBA APB or a generic memory mapped interface.


    Device Utilization and Performance

    I2C-SMBUS megafunction reference designs have been evaluated in a variety of technologies. The megafunction configured with an APB interface and the optional timer instantiated uses 281 ALMs in a Cyclone V device.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportN/A
    User InterfaceOther: 8-bit generic; 32-bit APB
    IP-XACT Metadata includedN
    Simulators supportedModelSim, Questa, NC-SIM
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    If No, is it planned?N
    IP has undergone interoperability testing
    Interoperability reports available  N

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